NXP has revealed further details of its stand-alone ARM Cortex-M0 microcontroller.
“The device we are showing at the Embedded Systems Conference in Silicon Valley next week will be fully-functioning silicon with all the peripherals working,” NXP microcontroller head Geoff Lees told EW.
If he has silicon now, why wait for the scheduled release date in 2010?
“For the rest of this year we will be working with lead partners,” said Lees, “and flash adds a lot of complexity to the process. It needs a lot more qualification than standard CMOS.”
Third-party tool vendors need time to develop products including “almost free evaluation boards”, he added. “And a lot of application code needs to be written, and drivers.”
"M0 controllers at NXP will be made on 0.18 and 0.14µm processes for the best combination of operating current and leakage,” claimed Lees, giving an operating range of 1.8 to 3.6V.
“In future we are looking at techniques to go below 1V over the next two to three years,” he said - also revealing that an on-chip boost converter for single cell operation is also being considered, but not for the first tranche or products.
See ARM Cortex-M0 - How it works
The firm has dubbed its family LPC1100, and it will be introduced with up to 128k flash and 16k RAM to compete with 8 and 16-bit microcontrollers.
Cortex-M0 is a simple 32-bit controller touted by ARM as a replacement for 8 and 16-bit controllers where communication stacks or long word lengths have to be handled.
The core has been designed for low-power operation from the out-set, leaning it towards integration in asics for portable products.
NXP plans to do this, but also sees stand-alone M0 chips appearing in mains-fed applications - for example as a low-power controller to manage stand-by in set-top boxes and TVs.
In these applications, said Lees, the M0 has enough processing power to manage the product in operating mode as well.
One interface planned for the LPC1100 family is an I2S bus which can transfer stereo to an audio codec.
According to Lees, NXP is one of the companies that prompted ARM to release the M0 design.
NXP had already adopted version two of ARM’s Cortex M3 design. “We were looking for a higher performance, lower power alternative to the ARM7 and were impressed with version two of the Cortex M3. It added a wake-up interrupt controller and software power-down,” said Lees.
“It has an improved memory interface compared with the first M3, and although the target was 80MHz, we got 100MHz from first silicon. We are demonstrating a 120MHz M3 next week,” he added.
NXP was also looking for a 16bit replacement processor and, according to Lees, went to ARM with a request for a cut-down M3. It turned out that there was already a research group working at ARM on what became the M0 and the NXT request helped ARM to decide to commercialise it.
The M0 executes the same Thumb instructions that the ARM7TDMI, plus a few others. “The instruction set means that all of our ARM7 and ARM9 customers can use their existing tools. They don’t need to buy a new C compiler. And they can use new features by adding in-line code to the C,” said Lees.