National Semiconductor is claiming a world record for its 3.6Gsample/s 12bit A-D converter.
"It is the fastest 12bit available," Paul McCormack, product marketing manager at the firm told EW. "The ADC12D1800 is 3.6 times faster than any other available 12bit device."
Designed at the firm's Munich office, the chip has been made on National's in-house 0.18µm CMOS process. "It is just CMOS cells," said McCormack, "no bipolars and no exotics like SiGe."
The device can be pin selected to operate as one 12bit 3.6Gsample/s converter, or two 12bit 1.8Gsample/s converters.
"There are two converters, interleaved internally," McCormack explained.
The architecture is folding and interpolating which is similar to the flash architecture, but re-uses comparators in several stages.
In flash converters there is a single bank of one-comparator-per-output-level - over 4,000 for 12bits.
With far fewer comparators, the converter takes less power and occupies less die area.
However, because banks of comparators are reused, the conversion latency is longer than a flash converter - in this case, 13, 13.5, 14 or 14.5µs depending on demultiplexing ratio - see below.
Dynamic performance is: -147dBm/Hz noise floor, 52dB noise power ratio (NPR) and -61dBFS intermodulation distortion (IMD).
"The internal track-and-hold amplifier and self-calibration scheme enable a very flat response of all dynamic parameters for input frequencies exceeding 2GHz, while providing an 10-18 code error rate," said National.
The device is aimed at software-defined radios and can ingest the whole DC to 2.8GHz band through its 100Ω differential front-end.
Should buffering, single-ended to differential conversion, level shifting, or gain be required, the 2.8GHz bandwidth LMH6554 SiGe bipolar amplifier is available.
Data throughput is such that most DSPs would be swamped by the 12x3.6Gsample/s output.
"In most applications, the output of the ADC will go to an FPGA for digital down conversion before the DSP," said McCormack.
Although the output can be configured to deliver 12 bit of parallel data at 3.6Gbit/s, to ease data handling the chip has 96 LVDS data outputs on 192 pins.
"Operated as two converters across 96 outputs, the data rate drops to 900Mbit/s," explained McCormack.
Intermediate de-multiplexing values can be set, with the de-multiplexers delay being responsible for the device's variable latency.
Power consumption is 4.1W at 3.6Gsample/s, dropping linearly through 3.4W at 2Gsample/s
Applications are foreseen in satellite receivers, microwave backhauls for phone basestation, radar, and optical links.
"In next-generation multi-channel set-top box applications, one ADC12D1X00 can replace all of the tuners," claimed National. "Shifting such architectures to software-defined radio dramatically reduces board area, power consumption, and cost, while significantly improving system flexibility."
The ADCs run off a single 1.9V rail, and there are two slower versions: ADC12D1000 and ADC12D1600, offering 2x1 and 2x1.6Gsample/s respectively.
"They include circuitry for multi-chip synchronisation, programmable gain and offset adjustment per channel," said National.
Devices come in 292 ball, thermally enhanced BGA packages which are pin-compatible with the earlier 10bit ADC10D1000 and ADC10D1500.
Space-qualified version will be supplied in a hermetic 376 column, ceramic column grid array that meets radiation levels of 120MeV for single event latch-up and a total ionizing dose of 100Krads.
Production quantities are scheduled for the third quarter of 2010.
Price has yet to be disclosed.
