The optimum board design needs an integrated approach to SI, PI and EMI, say Aki Nakatani and Hiroshi Higashitani
There are many standards for high-speed serial signalling such as HDMI, PCI Express, Serial ATA, and DDR memory. The higher speeds give rise to greater demands on printed circuit board designs to meet power signal integrity (SI), power integrity (PI), and electromagnetic inference (EMI) specifications.
SI, PI and EMI design used to be considered separate disciplines, each with its own design rules, analysis methods, and measurement techniques. A more modern approach is to recognise that there is a strong interdependence among the three, and that optimum board design requires an integrated approach.
A signal integrity problem, for example, may lead directly to an EMI problem. This article provides a summary of the important design considerations and presents an LVDS case study for integrated signal integrity, power integrity and EMI design.
Reducing EMI/EMC problems early in the design cycle using a virtual design process has been a dream for many engineers fettered with the problem of fixing complex coupling issues on nearly finalised designs.
Working together with Panasonic, Ansoft has created a reliable methodology that enables virtual design for today's complex EMI/EMC problems.
A reference design board for a consumer electronics device is used as an example to illustrate how to accurately predict and suppress board resonances and resulting radiated emissions.
The design flow proposed illustrates how to use 3D electromagnetic extraction together with advanced circuit simulation and common EDA layout tools to pin-point the problems before the actual production of the board. Insight provided by simulation will be highlighted, design changes that address these issues will be made, and the new design will be re-simulated.
Proper measurement techniques will be shown and discussed. Results that validate the method and compare the simulated and measured results for the original design as well as the improved design will be shown.
Identifying potential problems
Using a complementary suite of analysis tools, the full LVDS channel was modelled. The channel included three PCB's (video, mechanical controller, and CPU) and two Molex FFP/FPC surface mount connectors. Full-wave Spice and S-parameter models were extracted for the PCB's using 3D electromagnetic simulation tools. W-element and 2.5 D planar models were created for the connectors. The individual models were inserted into a circuit simulator to form the complete channel.
With the full channel assembled, the circuit simulator was then used to create a channel impedance map akin to a time domain reflectometer (TDR) result. The system's initial design had a significant impedance problem along the video board.
Upon further examination of the video board's layout, a pad and via were determined to be the root cause (Figure 1, p14). The impedance mismatch was the result of a step change in the width of the trace near the via. In addition to the impedance mismatch, it was determined that the original trace routing would also lead to skew. The skew and impedance mismatch were addressed in two steps.
First, the trace routing was reconfigured so that the total length of each trace in the differential pair was made equal. This was accomplished by overlapping the traces. The impedance mismatch, on the other hand, was resolved by eliminating the width step change in the routing to the via and by optimising the pad and antipad radii. The pad and antipads were adjusted by parameterising their respective geometries in a 3D electromagnetic solver (HFSS) and running an optimisation program (Optimetrix).
Once the optimal routing and via geometries were identified, the engineers focused on the impedance peak of the FPC connector. Polyamide strips were placed on the surface of the connector over certain sections. With their higher permittivity, the polyamide strips cause the local electric fields to be more tightly concentrated.
Finally, a common mode noise filter was added to the circuit to reduce common mode signals while permitting differential signals.
Reduction in EMI
By addressing the SI problems in the PCB's and the connectors, the designers confirmed they had improved the channel's EMI performance. In the initial design, the LVDS signal will be scattered whenever it encounters an impedance discontinuity. The scattered energy has to go somewhere.
Some of the energy scatters back toward the transmitter; some of the energy couples to other propagation modes, especially common mode; and, still other energy can couple into parallel plate resonant modes within the PCB. This energy can then radiate to produce unwanted EMI.
Solving the SI problem therefore has a direct affect on the radiated emissions of the system. Laboratory measurements of the network camera's radiated emissions before and after the SI modifications clearly shows a reduction.
Aki Nakatani, Ph.D is from Ansoft and Hiroshi Higashitani, Ph.D is from Panasonic Electronic Devices