Soitec, the SOI wafer specialist has joined Sematech the US technology development programme to develop processes using SOI and other high-performance, low-power IC applications.
Fully depleted SOI presents advantages in variability control and cost reductions at the 28 nm technology node and beyond.
Soitec will join the work at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany, working on metrology, materials, process technology, and device characterization to extend CMOS and high-mobility FinFET technologies.
Specifically, the plan is to develop dimensional and films metrology on Soitec’s SOI wafers.
The programme explores materials, transistor structures, and alternative non-volatile memories to help accelerate innovation in the continued scaling of logic and memory applications.
“Soitec’s expertise in substrate fabrication methodology will complement our own device and process expertise as well as enable us to offer our experience in developing leading-edge metrology capabilities to characterize these advanced devices and evaluate critical defects,” says Raj Jammy, Sematech’s vice president of emerging technologies, “we will work together to develop practical and promising high-mobility non-planar and metrology approaches to speed the transition of these new innovations to mainstream semiconductor production.”