Renesas Technology’s 32-bit microprocessor plans have started to take shape.
The first RX family microcontrollers built around the RX CPU have been introduced alongside a pair of dual-core SH processors which are sampling now and which will be generally available later in the year.
The multicore processor plans follow two courses. One is the SH7205 family of industrial MCUs based on SH-2A cores running an asymmetric multi-processing (AMP) architecture.
Announced in November, the SH7205 has two 200MHz cores achieving 960DMIPS and with two CAN channels, 8-channel 10-bit ADC and a pair of 16-bit timers its main application will be motor control.
The second course is represented by the new SH7724, which is a system-on-chip device based on 500MHz SH-4A cores capable of running Linux in a symmetric multi-processing (SMP) architecture.
It has separate video and audio processors as well as Ethernet, USB2.0 and SDHI interface support.
“Our dual-core strategy is not just about the performance gains it is about running dual applications on the one chip,” said Robert Kalman, marketing engineer at Renesas.
A feature of the AMP architecture is that it assigns certain tasks to each processor rather than sharing processing between the cores symmetrically as in SMP.
For the real-time motor control and safety critical industrial applications for which the SH7205 is intended an SMP multiprocessor architecture is not suitable primarily due to the complexity it introduces in the debug of a multi-state architecture.
“SMP is not ideal for industrial applications,” said Kalman. “There is not much support of the RTOS in SMP and it is still unusual for someone to run safety-critical applications on Linux.”
See MPC Data and Renesas Little Blue Linux development kits
The other part of the strategy is the single-core RX CPU which implements a complex instruction set computer (CISC) architecture that has been in development for two years and is intended to unify and be compatible with the two cores which are the basis of the company’s H8 and M16C microcontroller lines.
Eventually the RX family of devices will consist of a range of 32-bit MCUs, the RX600 series, and a range of lower power 16-bit devices, the RX200 series.
The first eight 32-bit MCUs in the RX610 family deliver 1.65MIPS/MHz processing performance operating at speeds up to 100MHz.
The MCU’s operating power consumption is 0.5mA/MHz.
RX610 MCUs have up to 2Mbyte of on-chip flash memory that can be accessed at 100MHz in a single clock cycle to maximise code execution.
They also provide 32kbyte of data flash memory with a background operation function that enables data to be written at the same time a program is executing.
In the pipeline is the companion RX200 family, which will be optimised for low-voltage operation.
Also in the pipeline for later this year is another SH-2A based chip, a graphics controller with 1Mbyte of SRAM to act as an on-chip frame buffer. “This is four times as fast as when using off-chip SRAM,” said Kalman.