Moore’s Law has become an industry-wide challenge – our de facto industry promise to pursue integration as far as physics and a reasonable cost structure will allow.
This should continue for many years, if we can meet and collaboratively overcome some key challenges in power consumption, manufacturability, and complexity.
Generally speaking, however, as feature sizes get smaller, problems get proportionately bigger.
Problems like signal integrity, crosstalk, defects, proximity effects, timing delays, thermal effects, leakage, packaging, copper pooling, and pattern fidelity.
It would be fine if it were just a matter of identifying and fixing these defects in manufacturing, as was the case a few generations ago. But in today’s competitive consumer market, IC companies and their downstream customers cannot afford a respin. We have to be able to anticipate and fix these problems before they occur.
This has challenged EDA companies to develop key design for manufacturing (DFM) technologies, including extremely accurate modeling solutions for both mask-making and manufacturing.
Power
Another area with multiple challenges is power consumption. It has always been critical in designs for mobile applications, as there is a need to better manage power of multiple cores running computation-intensive applications like video, and multiple RF radios for sometimes simultaneous communication.
At the other end of the spectrum are the fixed-location datacentres which, multiple studies suggest, are increasingly inefficient systems.
Designers are playing an increasingly important role in improving this outlook. In any industry, “going green” has to start somewhere, and in the $30 trillion electronics ecosystem, going green starts with chip design.
EDA solutions such as the Common Power Format have enabled the quick adoption of new power-efficient design methodologies that capture low-power design intent, increase designer productivity and enable greener technologies.
At the same time, they can result in less expensive packaging and heat dissipation technologies. This can be a significant saving, as some thermal packaging technologies can cost up to 100% of the cost of the chip itself.
Circuit density
One of the most striking trends is the escalating number of processor cores being integrated into all kinds of products. The ITRS roadmap says there will be dozens of cores in the typical SoC (system on chip) by the end of the decade and approaching 100 cores in the five years to follow.
Some would say that is conservative, but more importantly from an EDA perspective, somebody has to design them.
Another broad trend is the inclusion of analogue and RF circuitry in virtually every SoC-scale design. Mixing high-speed digital with sensitive analog can generate many challenges at the chip level. The task of combining all of this diverse functionality onto a single chip, while maintaining design intent, is increasingly enormous.
At the same time, the computational burden of creating, managing and analysing the vast amounts of data needed to capture the design is also increasing at an alarming rate.
To keep pace, EDA tools have to support multicore processing systems from start to finish.
Increasingly, EDA companies must collaborate with other companies in the semiconductor ecosystem to ensure these complex projects can be delivered quickly and with the best possible results.
Steve Carlson is a v-p at Cadence Design Systems