Synopsys has extended its verification collaboration with Freescale to look at ways of managing the cost of chip design verification.
Typically it is assummed that IC design verification can account for up to 75% of the total cost of product development.
"Functional verification comprises the largest portion of our total cost of product development and has a greater impact on our production schedules than any other single factor," said Dan Cronin, v-p of hardware R&D, Network Solutions Division at Freescale Semiconductor.
The work with design tool firm Synopsys is expected to address the efficiency of compute farms and productivity of engineers.
Freescale was an early adopter of SystemVerilog, the unified hardware description and verification language (HDVL) standard.
Designation IEEE 1800, it is an extension of the established IEEE 1364 Verilog language and was originally developed by Accellera to improve productivity in the design of large gate-count devices.
"Our collaboration is now extending beyond this standard. With verification becoming a larger part of overall product development cost, we are collaborating with Freescale to deliver solutions that help manage the total cost of verification," said Manoj Gandhi, senior v-p and general manager, Verification Group, Synopsys.