Colin Dente is currently CEO of Akya, the privately held dynamically reconfigurable logic company based in the UK. He has previously worked as Akya’s VP of Engineering for several years.
It's fairly non-contentious to say that there's currently a desperate need for higher levels of abstraction and radically shorter design times in IC production. I think that's hit home to just about everyone by now.
As I mentioned in an interview with Electronics Weekly some weeks ago this problem is crippling the electronics industry. When you look at the cost of developing a new chip there's a strong temptation to say "we're doomed".
We're approaching the point now where there's no chance for small companies with a 'bright idea' to come up from beneath the big boys. Instead, success is becoming more-and-more a matter of throwing vast amounts of money at huge teams of designers and verification engineers simply to be first to market in a design environment that is slowly stagnating.
DRL
My own interest in this area is focused on the dynamically reconfigurable logic (DRL) technologies that I work on.
DRL is a perfect example of a technology that has, in the past, been slow to get off the ground due to lengthy design times. While we've worked on developments that significantly improve the design times of DRL technology it's nonetheless of benefit to the whole industry to work together to reduce design times further.
No technology sits in isolation but instead every IC technology affects every other; in the availability of tools, new processes and the cross-fertilisation of knowledge.
RTL
It's well-known that the productivity of RTL designers lags hopelessly far behind the ever-expanding gate counts of modern chip processes (the so-called 'design gap'). But design times are only part of the problem. The industry also has to lower the amount of time it takes to verify a design from the current absurd levels of around 70% of the total development time.
One way to improve design times includes adopting a high-level synthesis approach such as SystemC-based flow. Others choose to work to develop or use other abstract and flexible design methods, (my company took this approach with the ART Architecture Description (AAD) DRL design language).
Lowering design times is ultimately all that matters, not which approach you take, and companies should simply adopt whichever works best for them.
Verify
Designers need a better way to verify than the current RTL-based techniques. Even if you're not using high-level synthesis flow then transaction-level modelling (TLM) techniques can still be applied to improve verification by giving designers an executable design at a much earlier stage, allowing verification to be performed in parallel with the design process, and at a much higher level of abstraction.
It's important to realise that early, high-level verification gives you two huge benefits.
Firstly, by having an executable model early on in the design process, you're able to verify that what you're designing is going to do what you want it to design: It answers the question "have I designed the right thing?"
If you have to wait until the design is finished, as is the case with current RTL flows, you can only check for errors in your implementation. This only answers the question "have I designed the thing right?" This is a fundamentally different question. Answering the right question early on in the design process can make the difference between success and failure of a project.
The second major benefit of early high-level verification is massively reduced run times for verification. With a properly designed verification strategy, much of the verification that is performed at a high-level does not need to be repeated later on. This means that verification performed on abstract, untimed models, running tens or hundreds of times faster than the equivalent RTL models is used instead of RTL verification.
Industry to cooperation
Of course, verification of systems using high-level models needs the industry to cooperate on the generation of models and verification IP, and this is where industry standards such as UVM (the Universal Verification Methodology) come in, providing a consistent framework for the development and use of verification tools, languages and IP.
The design industry has to get past this design and verification impasse or risk losing the very things that made it so successful in the first place; competition based on design creativity and breakneck innovation.
Your boss may tell you that you can't risk changing your design methods and that existing RTL design is working fine. If so they're a dinosaur; and you can tell them I said so.
Colin Dente is currently CEO of Akya, the privately held dynamically reconfigurable logic company based in the UK. He has previously worked as Akya’s VP of Engineering for several years. Prior to this Colin worked as Technical Director for NEuW Limited. Colin has a long history in complex semiconductor design. With a strong background in technology for the telecoms industry, he has a wealth of experience emphasising the need for designs that are small in size and highly power-efficient.
Akya provides dynamically reconfigurable logic IP. Its products enable the development of future-proofed semiconductors with a highly efficient use of silicon area.