The JTAG/boundary-scan test and programming tools have traditionally been seen as costly and complex to implement. As a result, much of their use to date has been limited to the testing or programming of boards on the production line.
This is an outdated view and is at odds with what test system suppliers are offering in the JTAG/boundary scan market.
The cost of implementing boundary scan is falling.
According to James Stanbridge, sales manager at JTAG Technologies, although JTAG/boundary scan is perhaps best known as a structural test tool for use during PCB manufacture, this is not the whole story.
“JTAG/boundary-scan has for many years been used to verify the connectivity between JTAG-compliant (and some non-compliant) devices on boards and also for CPLD and flash in-system programming,” says Stanbridge.
MBDA Missile Systems
Stanbridge gives the example of engineers at defence company MBDA Missile Systems, who found that with projects seeing the availability of hardware much earlier than firmware, there was often a lull during a project before peripheral circuits could be verified.
“Encouraged by their test department, one group of hardware engineers in MBDA picked up JTAG debug for the first time,” says Stanbridge.
The design in question features two FPGAs (an EPM240T and a LC4512V) in a single boundary scan chain; and approximately 50 device “clusters” are either controlled or monitored by the FPGAs.
“As the company already owned a number of compatible boundary-scan controllers, it was an easy decision to use one in conjunction with our Buzz tool, downloaded from the internet to debug the hardware,” says Stanbridge.
Suitable break-out boxes/leads were used to access power and stimulate/monitor the board.
With the tool running on a laptop, the boundary-scan description language (BSDL) models of the two FPGAs were downloaded from the manufacturers’ websites.
“Within minutes, MBDA’s engineers were able to confirm the [scan-path] infrastructure of the board, confirming the functionality of the JTAG boundary scan chain,” says Stanbridge.
All interconnects between the FPGAs were tested, driving outputs high and low and ensuring the corresponding inputs followed.
The engineers could also check that all the free-running clocks were operating correctly.
“By using the free tool and some basic JTAG controller hardware, MBDA engineers were able, over a period of just two days, to prove the manufacture and electronic integrity of a new hardware design,” says Stanbridge.
Board test
Even in the area of board test there seems to be growing interest in the use of boundary scan.
“What has changed is the message that boundary scan can complement and not necessarily compete with existing in-circuit test [ICT] equipment,” says Karl Miles, sales manager at Goepel Electronics.
The message from the test firms is that boundary scan can be implemented painlessly within existing test environments.
“With systems incorporating embedded processors and FPGAs, there is clear potential for boundary scan,” says Miles.
“And there is now an awareness that it can be implemented as part of existing test functions.”
For example, says Miles, boundary scan is being used to program FPGAs and Asics in parallel within a Teradyne test set-up, which resulted in a reduction in programming time.
Another example of how JTAG/boundary scan is being used in a semiconductor design environment comes from King’s Langley-based processor IP developer Imagination Technologies.
The chip firm is using the XJTAG boundary scan system in the development of system-on-chip (SoC) devices for the mobile phone and in-car electronics markets.
Typically, these designs feature high I/O interconnect density with complex FPGAs and many signals running on internal layers that could not be probed.
“We recognised the need to move from socket-based testing to a boundary scan-based system,” says Mark Dunn, v-p engineering in Imagination Technologies’ IMGworks group.
Greater functionality
Imagination Technologies is using the XJTAG boundary scan tool to test and debug prototypes, test assemblies and customer development boards.
“It has much greater functionality than we expected and we can test memory interfaces and non-JTAG components well beyond the scan chain – making the system very flexible for debugging in the laboratory,” says Dunn.
Test scripts
One benefit is that the boundary scan tool allows for the compilation of test scripts before the hardware is ready.
“We see the trend of increasing use of FPGA based system-on-chip designs with embedded processors, high-complexity functions, and high-speed peripherals continuing in the future,” says Bettina Richter, marketing manager at Goepel Electronics.
For example, says Richter, our VarioTAP emulator and model library opens up new opportunities for board-level test and in-system programming for users of Xilinx devices with integrated PowerPC cores.
“These new VarioTAP models allow our customers to first program the FPGA and then to combine structural boundary scan tests, dynamic emulation tests, mixed-signal tests, and flash in-system programming in one platform,” says Richter.
“This concept not only improves the JTAG/boundary scan fault coverage considerably, but also enables significant cost reductions in production test.”