Guest columnist Shabtay Matalon, ESL market development manager for Mentor Graphics Design Creation and Synthesis Division believes that designers looking to power optimise their systems should focus on the electronic system level (ESL).
The conflicting demands for feature-rich, high-performance devices and long-running, cool-operating products threaten to violate market-driven power requirements. As process technology evolves and chips become larger, increases in the power consumption trend will surpass the low power targets for designs. Consequently, the need to optimize for power is more urgent than ever.
The greatest opportunity to accomplish this is at the architectural level because downstream optimisation techniques are not nearly as effective. Real-world use cases have shown that power usage can be reduced by 80 percent at the electronic architectural level, compared to 20% at the RTL and 10% at the gate level.
Electronic system level (ESL) application-aware design methods make this significant reduction possible by shutting down idle power domains and by dynamically scaling voltage and frequency to the application performance requirements.
These opportunities for power optimisation are dependent on being able to understand how the application software running on the hardware impacts power consumption. Once the architecture is set and the design is implemented at the RTL, many of these opportunities to reduce power are foregone, as the design cannot be simulated fast enough in the context of the end-use application and major changes to the architecture become too expensive.
Figure 1: Architectural power optimisation better than that of lower levels of abstraction.
ESL design methods allow designers to rapidly characterise a system and create an architectural reference platform. ESL offers the advantages of simpler yet accurate executable models of the system, allowing extremely fast simulation (100x to 1000x faster than at the RTL), architectural exploration, and virtual prototyping. Visibility into system performance at the ESL enables designers to optimize power while making sure that critical performance requirements are still met.
There are four ways to optimise power savings at the ESL:
1. Optimising power with respect to system workload over time
2. Addressing hardware/software architecture tradeoffs
3. Optimising the system architecture configuration for area, performance, and power
4. Tuning the application software
Correlating power with the actual work done by the system provides the largest opportunity for optimising power. Simulation speed is critical in creating models that can actually simulate the system-level scenarios required for this kind of optimization.
Transaction-level models that contain static and dynamic power information enable designers to simulate real system use cases two to three orders of magnitude faster than at the RTL. Only by running them this fast can the true system workload be simulated and the power optimisation opportunities identified.
ESL design methods allow designers to quickly evaluate various hardware/software configurations to determine the best partition of functionality across hardware and software. Hardware implementations generally require less power because they are more efficient than running the same functionality in software.
The fast simulation of transaction-level models permits designers to run multiple, realistic, application-software-generated scenarios and evaluate power consumption for various design configurations under each scenario, identifying the configuration settings that provide the largest power savings.
Optimising area, performance, and power is significantly easier and more effective using transaction-level models because design functionality is not changed when exploring different architectures and timing constraints. Thus, designers can measure the power of different configurations to see which results in the best tradeoff between power and performance requirements.
Figure 2. Power analysis of various configurations of the same functionality revealed a 10x power variation in the IFFT block alone when implementing the same IFFT function. (Source: “802.11a Transmitter: A Case Study in Microarchitectural Exploration,” N. Dave et. al., Proceedings of MEMOCODE 2006)
Application software can be tuned to achieve lower power usage by comparing the power profiles of different software routines running on the same platform and by using different compiler options for the same application software. As different software applications running on the same platform can produce a wide variation in power consumption, it is very important to simulate the platform with the final application software running on the device.
A mechanism is needed to facilitate all four of these architectural power optimisation approaches. The best means to this end is a scalable transaction-level modeling methodology for writing ESL models in compliance with the SystemC TLM2.0 standard.
A single, scalable TLM2.0 model handles all ESL abstraction levels and design tasks because it separates communication, functionality, and the architectural aspects of timing and power into distinct yet synchronized models. Scalable transaction level models allow timing and power details to be added, changed, or disabled as needed while maintaining a single behavioral description throughout the design flow. This has an enormous impact on productivity, quality, and optimisation by simplifying code complexity and by making it practical to make frequent changes to a design.
Because a power model cannot be defined without the context of timing, timing and power are inextricably linked in a transaction-level model. Power consumption over time is impacted by how transactions are propagated throughout the design and by key design implementation considerations. Scalable power models support transaction-level modeling of all power types (dynamic, static, and clock tree), and they allow the timing and power analysis toolset to quickly capture a wide range of timing and power information during simulation and feed it into the performance and power profile graphs.
Scalable TLM2.0 models enable designers to test the validity of their power budget estimations and refine them as they progress through the design flow. Because the process technology is not always known beforehand, an ESL low power solution must support modification and simulation of IP models using different process technology assumptions. This allows designers to evaluate which process technology will meet a design’s power requirements.
Finally, because new designs consist of both new blocks and reusable IP, any power optimization approach must allow mixing the more precise power models for existing IP with the less precise, estimated power models for new blocks. This allows designers to focus their optimization techniques on the new portions of the design while evaluating the impact of existing IP on power.
Architectural analysis, exploration, and optimisation of power and timing at the ESL, supported by transaction-level modeling of timing and power, enables designers to achieve up to 80 percent power reduction at the architectural level. Further, extremely fast simulation of transaction-level models makes it possible to run realistic system-level scenarios and quickly explore the impact of multiple scenarios on the power of the device.
Therefore, design teams will know what the realistic power consumption is going to be with respect to system workload over time, and they will enjoy significantly larger opportunities to reduce power. It’s clear that only by moving up to the ESL can designers reconcile the conflicting demands for more functionality, more performance, and less power.