UMC is the latest foundry to announce that it has manufactured first fully functional 28nm SRAM chips.
The chips are based on a low-leakage process using advanced double-patterning immersion lithography and strained silicon technology. The feature size of a six-transistor SRAM cell is approximately 0.122 micron square.
The advantage of double patterning is that each mask has more room for optical proximity correction (OPC), adding computer-calculated shapes around features which compensate for the blurring that occurs when the features are smaller than one wavelength. OPC is used in single-exposure lithography at 90nm and below.
A disadvantage of double patterning is that it requires more than twice the positioning accuracy. Typically, 32nm double patterning requires 2nm positioning.
According to S.C. Chien, v-p of advanced technology development at UMC: “We are excited about this latest achievement for 28nm, as it provides a solid starting point for further development of this technology node towards mainstream availability down the road. Improvements on areas such as minimum supply-voltage, modeling of strain effects, and natural yield will be our focus going forward.”
The foundry uses conventional silicon gate/silicon-oxy-nitride gate oxide technology for its low leakage process, which is ideal for portable applications such as mobile phone ICs.
A second process option will use a high-k/metal gate stack for speed-intensive products such as graphic, application processor, and high-speed communication ICs.
UMC will also provide foundry services for customized 32nm technologies based on its 28nm process platform.