Lattice Semiconductor has significantly increased performance with its next generation LatticeECP4 FPGA family, which features a 6Gbit/s serialiser/deserialiser (SERDES) and new DSP capability.
Lattice believes it has a lower cost programmable platform with the performance for traditional FPGA applications in wireless basetstations and video systems.
The firm has also designed hardwired IP-based communications engines for wireless, wireline, video, and computing applications.
ECP4 FPGAs are up to 50% faster than previous generation devices and feature 1066Mbit/s DDR3 memory interfaces and 1.25Gbit/s LVDS I/Os that are also capable of being provisioned as serial Gigabit Ethernet interfaces.
"The ECP4family has 66% more logic resources and 42% more embedded memory," said the company.
The ECP4 FPGAs contain up to sixteen CEI-compliant 6Gbit/s SERDES channels with embedded Physical Coding Sub-layer (PCS) blocks in both wire-bonded and flip chip packages for highly integrated designs.
"The configurable SERDES/PCS can be seamlessly integrated with the hardened communications engines to economically build complete high bandwidth sub-systems," said the company.
"The communications engines offer up to x10 lower power and cost reduction of similar implementations in FPGA fabrics," claimed Lattice.
The ECP4 communication engines portfolio includes solutions for PCI Express 2.1, multiple 10 Gigabit Ethernet MAC and Tri-speed Ethernet MACs as well as Serial Rapid I/O (SRIO) 2.1.
The FPGA's DSP blocks incorporate 18x18 multipliers, wide ALUs, adder-trees and carry chains for cascadability.
New logic means each ECP4 DSP block can be equal to four ECP3 DSP blocks . "This enables up to x4 the signal processing capability of the previous generation LatticeECP3 devices," said Lattice.
The 18x18 multipliers can be split into 9x9 or combined into 36x36 and up to 576 multipliers can be cascaded together to build complex filters for wireless remote radio heads (RRH), MIMO-based RF antenna solutions and video processing applications.
There are intellectual property (IP) cores for CPRI, OBSAI, Serial RapidIO, XAUI, SGMII/Gigabit Ethernet, PCI Express, SMPTE for serial connectivity, FIR filters, FFT, Reed-Solomon encoders/decoders, CORDIC, CIC, NCO for DSP functions and several others for memory interfaces and connectivity.
ECP4 FPGAs will be designed with Lattice's Diamond 1.4 beta design software.
Device samples will be available in the first half of 2012 and high-volume production delivery is scheduled for the second half of 2012.
www.latticesemi.com/ecp4
A video demonstration of the LatticeECP4 FPGA Family can be viewed here