EnSilica has introduced a version of its eSi-RISC development suite which incorporates an FPGA-based hardware evaluation platform for its soft processor cores.
The evaluation platform is based on Altera’s Cyclone III FPGA with debugging facilitated through the Eclipse IDE and industry-standard GNU GCC 4.4.0 toolchain.
The toolchain features native support for the eSi-RISC architectural features.
FPGA configurations are supplied for the complete eSi-RISC processor family, along with examples of how the system-on-chip peripherals can be used, including a full port of the open source FreeRTOS with lwIP TCP/IP network stack.
“The ease and speed with which processors can be evaluated and applications developed and tested, plays an important role in developers’ choice of processors,” said Ian Lankshear, managing director of EnSilica.
Non-intrusive debugging for FPGAs is provided through the JTAG hardware debugger, which provides the ability to examine data, insert break and watchpoints and control program execution.
There is read/write access to all variables, registers, memory and attached peripherals, while supporting single-step and step-over execution of the C code and views of the disassembly.
The eSi-RISC Development Suite v2.1 also allows developers to debug code using hardware/software co-simulation by enabling remote control of Mentor Graphics’ ModelSim from the Eclipse GDB project debugger through a network socket connection.
eSi-RISC product information and downloads