A common challenge facing many semiconductor companies is the push for higher data transmission speeds to drive ever higher system performance.
When dealing with clock circuitry in processor and bus design, there are several design issues that must be overcome.
One of the main design issues in all applications is providing low phase noise or jitter. As the geometries of CMOS shrink, jitter becomes more of an issue. In consumer products, designers are looking not only for low jitter, in terms of phase noise, but also a cost-effective option. The semiconductor supplier needs to be creative, for example, providing in-circuit programmability or flexibility to ease development time. Yet still, there is the ever-present challenge to continuously increase system performance.
Increasing system performance is no longer as simple as revving up the frequency. System relevant qualities, such as signal integrity, noise immunity, jitter, integration and EMI (Electro Magnetic Interference), will define the overall system performance and eventually the system quality. The impact of any one parameter is no longer as crucial, it is the mix and the interaction of all parameters.
A good example is the demanding jitter requirements of the sample clock of an ADC, which is in the range of several 100fs. This extremely low jitter no longer can be met by simply using the system clock and route it to the ADC. In this case a clock refresher with jitter cleaning function, located next to the critical device and differential signalling is mandatory at a minimum. Sometimes additional bandpass filters and low-noise amplifier are needed to come down to such low jitter values. Also, a shielding mechanism may be needed in case cross-coupling or EMI is an issue.
How does this translate to clocks and clocking devices? Frequency, performance and flexibility (programmability) should help designers understand clocking requirements and lead them to more efficient and cost-effective clock architecture designs.
Frequency
Frequency is the “nuts and bolts” when talking about clocking devices, It means generation (create a new frequency), modification (frequency multiplication or division), adjustment (phase align, frequency synchronization, frequency modulation, accuracy) and distribution (multiple copies of a frequency). However, modifying the frequency may have an affect on clock quality and frequency accuracy.
Frequency generation always comes along with a phase-locked loop (PLL). A PLL translates an input frequency to the desired output frequency.
The pre-divider M and feedback-divider N of a PLL define the input-to-output frequency relation. If multiple simultaneous output frequencies are needed, dividers are placed in the output paths to create the required frequencies. In this case, the output frequencies are related by the divider values used. If multiple output frequencies are desired that are non-integer related, the generator must include multiple PLLs.
Synchronising time and frequency of events is essential in electronic systems. For example, it prevents divergence of audio/video data streams or minimises data loss in digital networks. Zero parts per million (ppm) clock accuracy is mandatory in systems where frequencies are created from one reference source.
If audio and video decoding is not synchronised (i.e. lip synch in A/V synchronisation), the viewer will notice that audible effects happen before or after they should. A potential solution for audio/video decode synchronisation is zero ppm clock accuracy.
Other non-zero ppm clocking issues are artefacts resulting from mismatched video rates in video/graphic display applications. Another important consideration is the effects when switching between frequencies, particularly the time spent by the PLL in achieving the new frequency.
Performance and quality of clock signals
All parameters derive from the performance and quality of clock signals and define the overall module and system performance. Critical performance parameters are jitter, phase noise, EMI, cross-coupling and signalling.
Jitter is a major performance parameter of PLL-based clock driver circuits because it directly impacts system performance such as data rate, signal-to-noise ratio or timing budget in memory systems. Jitter describes the stability of the clock signal in the time domain, similar to the phase noise specification in the frequency domain.
Spread spectrum clocking (SSC) is an effective method to reduce EMI in high-speed applications. It reduces the RF energy peak of the clock signal by modulating the frequency and spread the energy of the signal to a broader frequency range. As the energy of the clock signal remains constant, a varying frequency that broadens the overtones necessarily lowers their amplitudes. Doing this improves signal integrity within the board.
Cross-coupling in ICs occurs through interactions between several parts of the chip: between output stages, metal lines, bond wires and substrate. The coupling can be capacitive, inductive and resistive induced by output switching, leakage current, ground bouncing or power supply transients.
Flexibility
To generate, modify and fan out the user frequency and to mitigate potential “noise sources”, a large number of dedicated devices may be needed. Programmable clock devices could be an effective way to address the different requirements by one device only.
Using on-chip EEPROM technology, you can easily program and save the device’s settings in the EEPROM, so that no re-programming is required at power-up. In addition, the serial programming interface allows hot-programmability as well.
Clock device selection
Summarising all previously discussed findings, will give us the direction we know how an optimised timing device should look like:
Speed and frequency
- wide frequency range (0MHZ to 400MHz)
- multiple output frequencies from one clock source (PLLs and dividers)
- frequency stability and accuracy (high divider resolution)
- fast PLL lock time
Switching characteristics
- low jitter, low output skew, minimized coupling effects, stable duty cycle
- signal integrity, slew rate, SSC, EMI noise
- LVCMOS, LVDS or LVPECL (universal interfacing
Customisable and tunable
- quick upgrade without board/layout change
- dynamically re-programmable during operation
- configuration parameters can be stored/restored.
Two categories of clocking devices
CDCE706 and CDCE906 clock multipliers from Texas Instruments are designed to incorporate many of these features.
As timing requirements become more critical, a range of clock devices with different functions are available on the market. In principle, there is a need for two categories of clocking devices:
- function specific devices like jitter cleaner, clock recovery circuits or clock generator for DDR memories,
- flexible devices such as programmable clock generator, EMI optimiser, clock translator.
Albeit the latter do not belong to the top-performance category, they become more important for medium to high-performance applications. Programmable chips allow designers to customise the device, tweak the system’s clock features without redesigning the board, or have one device fitting for a several boards, and makes it ready for next generation design.
Georg Becke is CDC system engineer at Texas Instruments, Europe