Altera's growing interest in low power FPGAs now includes a range of Cyclone III devices with security features.
According to Altera, the Cyclone III LS FPGAs draw less than 0.25W of static power for 200K logic elements (LEs).
See: Cutting power consumption in complex FPGAs
The security features of the Cyclone III LS FPGA include anti-tamper, design-security and design-separation capabilities.
Intended for protecting sensitive data, the anti-tamper features include JTAG port protection, tamper monitoring, and cyclical redundancy check (CRC).
For a higher layer of protection, the devices feature an industry-standard AES 256-bit encryption key.
"Where size, weight, and power (SWaP) requirements are crucial, the design-separation feature of the Cyclone III LS FPGA enables high-assurance and industrial-safety applications in a single chip through logic, routing and I/O bank separation," said the company.
Military applcations are a target market for the device and in particular software-defined radio and crypto-subsystems.
The additional security features of the Cyclone III LS FPGAs give designers of secure communications applications the assurance that their information will be protected with anti-tamper technology.
See: Power fortunes: Estimating power in FPGA designs
Altera has also migrated its Cyclone III FPGAs to 60nm, and they now deliver 70,000 to 200,000 logic elements with a static power of under a quarter of a Watt.
Security has been boosted by two new features. One is a technique which 'zeroizes' the device if tampering its detected - i.e. it blanks the device, erases the memory and all the bits are set to zero.
The other new security technique is JTAG port protection which turns on in secure mode with only four basic JTAG instructions and with all the rest of the JTAG instructions hidden.
These two new security features are in addition to the two security features on previous Cyclone III devices - the 256bit Cyclone encryption key for the bit-stream, and having an on-chip oscillator as an uninterruptible clock source in the event tampering.
Further security, and redundancy, is provided by having physically separate design areas.
"You can put the design in two separated blocks", said Altera's Theresa Vu, "the military need physically separated design in the FPGA."
The chip can hold up to 8Mbits of embedded memory, and 396 embedded multipliers.
Asked why Altera had not put the device onto a more aggressive process than TSMC's 60nm LP process, Vu replied that to do so would have meant a re-design of the chip, while Altera had wanted to move fast with the device to get it to market in 14 months from product concept in March 2008 to shipping samples in June 2009.
Another reason for using 60nm is, added Vu, that leakage is better on the 60nm process than it is on the 40nm process.