France has become a world-class centre for silicon-on-insulator (SOI) wafer processing research.
Twenty years ago, SOI was a niche technology for military and aerospace applications.
Two French researchers at national microelectronics research institute CEA-Leti, André-Jacques Auberton-Hervé and Jean-Michel Lamure recognised the scaling and low power potential of the SOI process technology and set about making it commercially viable.
They founded Soitec at Grenoble to produce SOI wafers using a technique where an insulating layer is implanted in a standard CMOS wafer.
Michel Bruel, a colleague from CEA-Leti, patented a new method for making SOI wafers. Called ‘Smart Cut’, this new method involved shaving a very fine layer of silicon off one wafer and bonding it on to another, sandwiching the insulation between the top and bottom silicon.
This technique now accounts for a significant proportion of all SOI production wafers.
Soitec has become a leading producer of SOI wafers and is now developing process technology which will allow its customers to manufacture 22nm geometries.
The route that technologists at CEA-Leti have chosen is to fabricate fully depleted transistors on production CMOS wafers. They see fully depleted (FD) planar body transistors as the most effective way to 22nm SOI and beyond.
CEA-Leti has developed an advanced high-K/metal gate fully depleted SOI process as well as the design and simulation tools need for commercial chip production.
Potentially FDSOI technology could be used as an alternative to conventional bulk technology for process nodes 20nm and below.
“The electrostatic integrity of the transistors is ensured by the thinness of the body without the need for extra litho steps, like in the case of FinFETs, or of channel doping. The consequence is a planar technology that exhibits at the same time excellent short channel behaviour,” said CEA-Leti.
See: ARM sees first SOI processor taped out
Soitec is now in production of first sample wafers for the 22nm node at facilities in France and Singapore. The company said it is ready for ramp up with the needed capacity to follow market demand.
CEA-Leti has teamed with Circuits Multi Projects (CMP) to offer multi-project wafers based on the fully depleted SOI 20nm process.
According to Laurent Malier, CEO of CEA-Leti: “It is time now to enlarge the diffusion of the FDSOI technology enabling test cases on 20nm process and beyond.”
The first CMP run is scheduled to be launched in September 2011.
See: IBM: ‘World’s fastest computer chip’