Parsing software for the SystemVerilog language has been
developed by Verific Design Automation.
Licensing the parser would save a year or more of development
time to add SystemVerilog support to existing products, claimed the
firm.
"We have noticed in the second half of 2004 more interest from
digital designers in using SystemVerilog," said Michiel Ligthart,
v-p of operations at Verific.
But, he said: "Adding SystemVerilog is a huge undertaking, not
every company has the personnel or the funds to do this."
Verific's software includes a parser, analyser and elaborators.
The latter unrolls loops in the parse tree and produces a netlist,
much like a synthesis tool.
While the netlist is not optimised for any specific hardware, it
is useful to firms developing, for example, formal verification or
simulation tools.
The tool can process 10,000 lines of RTL a second on a 600MHz
Linux machine, said the firm.
Verific has sold its VHDL and Verilog parsers to firms such as
Altera, Infineon, Philips and Wolfson. "There are several smaller
EDA start-ups in Europe using our technology," said Ligthart.
Perpetual licences start at $100,000, while monthly licences are
$4,000. There are no royalties.
www.verific.com