STMicroelectronics claims it is the first to couple two ARM Cortex-A9 cores with a DDR3 (Third-generation double-data rate) memory interface.
Manufactured on a 55nm HCMOS (high-speed CMOS) process, the SPEAr1310 microprocessor supports both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent.
“This is the first device in the recently announced SPEAr1300 family and others will follow shortly,” said Loris Valenti, general manager of STMicroelectronics’ computer systems division.
There is an integrated DDR2/DDR3 memory controller and communications peripherals, including, USB, SATA and PCIe (with integrated PHY), in addition to a Giga Ethernet MAC.
Cache memory coherency with hardware accelerators and I/O blocks increases throughput and simplifies software development.
There is an accelerated coherency feature for hardware acceleration and better I/O.
Last September, ARM announced its first hard macro version of the Cortex-A9 processor which has been sold as soft IP since 2007.
Texas Instruments' OMAP 4 chipset platform for smartphones is based on a dual-core 1GHz ARM Cortex-A9 processor, but without a DDR3 memory interface.
See: ST to put ARM Cortex-A9 processor into HDTVs