US EDA firm Bluespec has released open source synthesis extensions to the SystemC language, enabling users to model, design and verify in the same environment.
The company said its ESL Synthesis Extensions (ESE) mean designers will be able to use SystemC to synthesise control logic and complex datapaths down to RTL.
The ESE products add measures (called ‘rules’ and ‘interface models’) to cater for concurrency and complex interfaces, offering significant improvements over thread-based techniques.
“Threads and events are too low-level to manage complex concurrency,” said George Harper, v-p of marketing at Bluespec.
Two versions are available – ESE for simulation of untimed, unclocked designs, and ESEPro for clocked simulations.
Bluespec was founded three years ago as a spin out from MIT. Its high level hardware description technology is based on a formal comparison technique called ‘term re-writing systems’ (TRS).
The firm's first product, Bluespec SystemVerilog, was released 18 months ago and uses the SystemVerilog syntax but with the addition of TRS, which speeds things up.
Bluespec