FPGA start-up MathStar, and Picochip which has an alternative technology to FPGA, have joined in the debate about whether FPGA start-ups, like Achronix, MathStar, Velogix and Cswitch, and alternative technologies like Picochip’s, can succeed.
The start-ups have all gone for very high performance parts to get away from the territory commanded by Xilinx and Altera.
“You can’t compete with Xilinx and Altera with an incremental performance increase, with something that’s 20 per cent faster or 30 per cent cheaper,” says Yousef Khalilollahi of Achronix, “our test silicon on 90nm runs at 2Ghz which is a four to five times improvement on the fastest Xilinx FPGA.”
However, Wim Roelandts, CEO of FPGA market leader Xilinx, says: “If there is a market for very high speed designs, I’d like to know about it. High speed is a small percentage of total sales.”
MathStar retorts: “Everybody knows that Xilinx and Altera are battling it out for the low-performance consumer market and, therefore, overlooking high-performance opportunities. Conversely, MathStar is quickly snapping up performance-demanding customers such as Honeywell (for military satellites), Alacron (for machine vision cameras), Adaptive Micro-Ware (for professional video). “
A big issue is whether the start-ups can create a sufficient body of place and route software.
“There is no third party place and route software”, says Xilinx’s Roelandts, adding, “the place and route software at Xilinx runs to 20m lines of code.”
Rupert Baines, vice president of marketing at PicoChip, which puts up a programmable array of 16-bit processors as an alternative to conventional FPGA, retorts: “A 20 year investment in place-and-route with 20m lines of code is no longer an asset: our equivalent has <10 man-years of investment but is >50X more efficient.”
At Achronix, Khalilollahi says: “Having a familiar architecture allows you to buy existing place and route tools, and modify them to fit the architecture, so long as the architecture is not so much out of whack with existing architectures,” says Khalilollahi.
At MathStar the response is succinct: “MathStar FPOA doesn't require timing closure”.
Another problem the start-ups will have to address is the issue of IP. Xilinx and Altera have spent years and hundreds of millions of dollars developing and buying rights to IP.
“Half of a Virtex 5 is an ASIC, and half is an FPGA”, points out Roelandts, “more and more we’re saying: ‘This is a framer’, or ‘This is for digital compression’, it’s no longer just silicon. We’re moving away from pure silicon sales to solution sales. We have architects who talk to customers’ architects.”
“MathStar is making significant progress with third-party IP vendors”, claims the company. It is working with Barco Silex of Belgium which has supplied MPEG2 and other codecs for the MathStar FPOA, and with Cadre Codesign Technologies of Canada which supplies MathStar and its customers with JPEG 2000 encoders.
Getting IP for the Achronix cores will not be a problem, reckons the company, because generally available ASIC IP will fit Achronix FPGAs.
“IP vendors have to modify ASIC IP for current FPGAs because current FPGA performance is so much worse than ASIC performance,” says Khalilollahi, “but our performance meets and exceeds ASIC performance, so we don’t burden them with the need to modify their IP. You just plug in the ASIC RTL code.”
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