ASIC design may come to end to an end at 45nm, killed by rising cost and lengthening time-to-market.
“I haven’t heard of ASICs at 65nm and there are not many 90nm ASICs at the moment because the costs are so high. Will they use 45nm when the mask sets will be an initial $2m to $3m?” asks Wim Roelandts, CEO of Xilinx.
Mask costs do come down over a node’s lifetime. The 65nm mask cost started at $2m and is now down at $1.5m. But the 45nm cost could be enough to kill off ASIC design at that node.
“There’ve been lots of attempts to revicve the ASIC marketlike ASSPs and structure ASICs but the design starts get fewer and fewer”, said Roelandts.
Agreeing with Roelandts is Professor David May FRS, Professor of Computer Science at Bristol University.
“If you’re building an ASIC device for a market in 2008 or 2009, which is what you have to do because it takes that long to design a complicated ASIC, you don’t know if the market is still going to be there when you’ve completed the chip”, says May, “and the cost of design is so high that people are becoming reluctant to fund complex ASIC designs and the number of designs has been dropping over the last 2/3 years.”
May’s answer is: “More generic technologies able to address multiple markets.” Roelandts’ answer is, naturally enough, more FPGAs.
Of course Wim would say so. He´s been saying so first at 90 nm and now at 65 nm. But he´s very good at his profession which is to say that the ASIC is dead.
But how do you define an ASIC? Is a baseband chip an ASIC? Its certainly application specific. And there are those already in the market.