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Parallel processing, Clearspeed, Picochip and XMOS

Parallel processing will be one of the key technologies under development this year with UK companies Clearspeed, Picochip and XMOS expected to play a leading part.

A good deal of interest in 2007 will be focussed on what comes out of XMOS, the company founded by the architect of the Inmos Transputer, Professor David May FRS, which received $1.2 million in late 2006 to commercialise a revolutionary new microprocessor design.

Not the least reason for the interest is that May is concentrating on parallel processor architectures, seen as the key technology now that the power density ceiling has flagged the end to serial processing architectures in high-end systems.

"It was 1972 when I graduated and artificial and intelligence and robotics had always been a fascination", says May, who is now Professor of Computer Science at Bristol University, "robotics is a parallel world. Robots do multiple tasks simultaneously. So my world was a parallel world."

25 years ago the Transputer brought a parallel processor architecture to the market which was widely admired and was used in massively parallel systems like radar and fingerprint analysis.

If you ask May about the XMOS architecture, he replies: "That's a closely guarded secret."

If you ask him what the world needs in terms of new microprocessor architectures he replies: "There is a need for a generic kind of platform, whether they are FPGAs and chips full of processors, or whatever"

This is the big issue in the electronics industry today. ""There's a lot of snake oil around in the multi-core business," says Alan Gatherer, CTO for communication infrastructure at Texas Instruments, "I'm not sure anyone knows how to build a generic multi-core architecture. It's a great goal, but the chances of failure are 100 per cent."

"A lot of the parallel processing start-ups have failed because they try to use a sequential programming language like C", says Peter Claydon, founder and COO of parallel processing chip start-up PicoChip, "the mentality of programmers is to expect everything to be serial. Multi-core is here to stay, but it needs a new way of thinking."

"The software guys don't move very fast. That's why multi-core processing looks as if it will be a long -term play", says John Goodacre, ARM's programming manager for multi-processing, "multi-threading was a stop-gap, but it doesn't add anything, and can make software very difficult to write."

"Customers say to us: 'Be very careful with parallel architectures'", says TI's Gatherer, "they ask us: 'You don't know how to programme these massively parallel devices yourselves do you?' That's one of the reasons why there's been no traction for those companies doing massively parallel architectures. These companies programme their own devices because no one else can. When they say: 'We've got a reference design so you don't need to programme it yourself', what they really mean is: 'We've got a reference design because we know you'll never be able to programme it yourself.'"

The problem is not in producing a multi-core chip. Multi-cores used for specific purposes have been common in the industry for years. The problem is producing a multi-core chip which works as a generic processor.

"We can produce a chip with a lot of theoretical MIPS but it won't be very programmable", says TI's Gatherer, "the difficulty is partitioning the programming across the cores. Our customers tell us that, if you have to partition an algorithm across multiple cores, and expect them all to talk to eachother in real-time, that's a hard problem."

"Inevitably there are going to be problems with multi-cores", says May, "the thing causing the most difficulty is that the core runs fast and the memory doesn't. When you try and put multiple cores on a chip sharing the memory, you have problems, because the memory is already running flat out."

"For the last ten to fifteen years what has been financed in the semiconductor industry is people doing very complicated ASIC in a specific market area", says May, "the problem is that, if you're building an ASIC device for a market in 2008 or 2009, which is what you have to do because it takes that long to design a complicated ASIC, you don't know if the market is still going to be there when you've completed the chip. And the cost of design is so high that people are becoming reluctant to fund complex ASIC designs and the number of designs has been dropping over the last 2/3 years. The answer is more generic technologies able to address multiple markets."

This will lead, reckons May, to the emergence of the IP-less companies which will understand both end-applications and how to programme platforms.

"We need engineers who understand the applications, and also know their way around programmable devices, and know how to programme the hardware," says May, "so I see growth in people rolling out generic technologies. There's no need for them to have their own IP. They configure the platform, they don't have to do hardware design or manufacture. It sounds like the ideal business to me. We all ought to be in it."

Can XMOS produce a generic, multi-core, programmable platform capable of being the catalyst for such a revolution in the IC industry?

Maybe 2007 will give the answer.


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Comments (3)

It seems like Prof. May is going to put together several lightweight generic RISC processors on a chip (either ASIC or FPGA) and to move the complexity to software using some type of new programming language... and it sounds like Occam! Or he will put in place some automatic conversion from C/C++.
What is not clear to me is how to solve the problem of the memory bottleneck.

JJO:

The problem of memory access is only one part of mapping io traffic / data flow to certain virtual instances, so indeed it is comparable to quantum computing where an instance presents multiple states at once. So the main issue is the correct synchronization between the multiple instances, which is part of the describing language. The actual memory technology TRAM or RLDRAM will be hidden by the appropriate memory access virtualization.

David is correct when he says that "Parallel processing will be one of the key technologies under development this year with UK companies Clearspeed, Picochip and XMOS expected to play a leading part."

Given our success with companies like Da Vinci Systems, who ship 48 Aspex Linedancer devices in a single system (4,000 processors per device) for their world leading colour correction systems together with 30+ other customers, I am sure we can also assist in getting UK Ltd on the parallel processing map.

Paul Greenfield
CEO, Aspex Semiconductor

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