Is there a design crunch coming up? Well, yes there always seems to be a design crunch coming up, but this time it’s a really mega-crunch, according to Kazuyoshi Yamada, the vice president and general manager, Custom SoC Solutions Unit, of NEC Electronics America.
According to Yamada, a 32nm SOC design will take 40 engineers ten years, or 250 engineers nearly two years.
What’s the answer? According to Rahul Sud, who designed the Inmos 16K NMOS SRAM which knocked Intel out of the SRAM business, and went on to found the E2PROM and programmable logic company Lattice Semiconductor, the answer is: logic foundries.
The semiconductor industry has encountered these ‘insurmountable’ barriers before, when rising costs have mandated a fundamental change in the industry’s business structure.
The last time it happened, argues Sud, is when the cost of fab reached half a billion. Start-ups couldn’t raise that sort of money, and many established companies couldn’t raise it either.
What came along to solve the problem? Answer: TSMC and the silicon foundry business model.
Suddenly the industry was off to the races again. The cost of funding start-ups dropped dramatically. Venture capitalists could afford to fund start-ups again. Medium sized companies could get their new chips built. The industry’s growth was resumed.
The same sort of innovative new business model, leading to a fundamental re-structuring of the industry, has to happen again, now that design costs are topping $50m.
" The industry has no choice, but to re-structure its business models again”, argues Sud, “and I foresee the birth of a new member of the semiconductor value chain namely the Design Fab, much like the foundry became a new member of the value chain in 1987."
“Design cost became unsustainable when the number of engineers required in the 80s for designing a complex SOC, went up by 40 times, from five in the 80s, to about 200 today, of which 100 are software and 70 are doing verification”, argues Sud, “that has to be multiplied by 2.5 times to reflect the 2.5 years required to design a chip today, compared to six months in the 1980s. So costs can reach $50m to $100m depending on complexity.
"The transformation of a fixed cost for a variable cost is”, argues Sud, “the same for a design fab as it was for a foundry".
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Comments (2)
Sounds interesting, but silicon foundries offer a common process for different designs (TSMC has maybe half a dozen processes at any given feature size, which share a lot of technology and expertise), but I have trouble seeing how this commonality would obtain in a design foundry. Are all the customers designing the same device? I don't think so!
Posted by Peter B | July 31, 2007 11:17 PM
Posted on July 31, 2007 23:17
I think the idea is that the design foundry would mostly be be doing verification
Posted by david manners | August 1, 2007 8:56 AM
Posted on August 1, 2007 08:56