"We're Going For It" - Spansion's Bertrand Cambou

First silicon was run in June. The first production run was in September. It is facilitised to run 500 wafers a week with the potential to be increased to 4,000 wpw and eventually to 7,500. So far Spansion has spent $600m on the fab, which it calls SP1.

The fab puts the seal on Spansion’s market-domination proposition – that it is the only company with a cost structure that can succeed in the NOR flash business.

“It’s the first time in the industry that’s there’s been a 300mm facility for NOR flash and it has been customised for Mirrorbit”, says Spansion CEO Dr Bertrand Cambou.

Mirrorbit is Spansion’s MNOS-based flash memory technology which is now used for 22 per cent of Spansion’s output. Mirrobit has, compared to the traditional floating gate technology used by rivals Samsung, STMicroelectronics and Intel, a simpler, cheaper manufacturing process which will scale quicker and further than floating gate.

This makes Cambou believe he can dominate the NOR flash market. Already the company has 32 per cent of the NOR flash market, according to WSTS, and the Mirrorbit portion took 22 per cent of that. Intel’s market share is 22 per cent.

“Intel don’t have a cost structure in place today to compete with us” says Cambou, “they lost $300m on revenues of $490m in Q2, and they lost $300m in Q1. They have to sell at below cost to compete.”

Nor does he think the new Intel-STMicroelectronics joint venture Numonyx will have any chance of success against Spansion.

“Numonyx is not capitalised. They have a $1.3bn loan but $900m of that has been paid to Intel and ST. They have 200mm fabs, their 300mm fab at Catania is an empty shell. They are using floating gate which is not scaling. They are losing money. Their strategy has to be re-thought”, says Cambou

Spansion has four cost advantages over its rivals:

The first cost advantage is the advantage of using 300mm wafers as compared to the 200mm wafers used by rivals. This advantage will continue to increase as Aizu moves into volume production on 300mm by the end of the year, while its rivals are stuck on 200mm. The cost advantage of 300mm over 200mm is 30 per cent, says Cambou.

The second cost advantage is an early move to 45nm. The move from 65nm to 45nm will improve cost by a further 50 per cent. This is due to happen late next year. “We will be the first NOR company to move to 45nm”, says Cambou.

The third cost advantage which Spansion has over its rivals is Spansion’s use of Mirrobit technology, compared to the floating gate technology used by rivals. That, according to Cambou, adds another 40 per cent cost advantage for Spansion over floating point rivals Samsung, and Numonyx.

And the fourth cost advantage is, according to Cambou, Spansion’s pioneering use of built-in self test (BIST) technology where you test the entire wafer, not each individual chip, which reduces cost.

Besides the four cost advantages, Spansion has a long-term advantage over it rivals because, according to Cambou, his rivals are trapped in a technology which won’t scale.

“I believe floating gate will be severely compromised below 45nm”, said Cambou, “it may do 40nm but if you go below that there’ll need to be big trade-offs.”

By contrast, Mirrorbit will scale to 25nm and beyond, reckons Spansion, which has a roadmap of 45nm production in 2008/09, 32nm in 2011 and 25nm in 2013.

And, further down the line, Spansion is nurturing a new technology which will double densities. That is its four-bit-per-cell technology which it calls Quadbit and which is expected to impact its mainstream product line in 2009.

It’s not surprising Cambou is feeling perky. “We’re going for it”, he says.