Synplicity’s Synplify DSP tool, which uses Electronic System Level Design (ESL) models for DSP synthesis, is achieving some considerable success, it seems.
Two customers have taped out SOC designs which used the tool, one chip was described as a ‘cell phone algorithm chip’ and the other described as ‘another wireless type of chip’ .
“Customers say they achieve an order of magnitude improvement in time to market”, says Synplicity’s Chris Eddington, “design is taking weeks instead of months, and changes take hours instead of days.”
Asked about the silicon efficiency of this approach, Eddington says: “The silicon efficiency is as good as hand-coded RTL. It’s resulting in a 10-15 per cent better area than hand-coded RTL.”
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