Gordon Moore always used to say he had never been able to see more than two process generations ahead, and this still seems apply, according to Toshiba Semiconductor's CEO, Shozo Saito.
“At this moment we're feeling good about the extension of 43nm to 32nm”, says Saito, “we start 43nm at the beginning of next year, and we have a good feasibility study of 32nm for 2009. The problem is that, after 32nm, we have some headaches.”
The first of these headaches is the floating gate structure itself. “At the moment the structure is floating gate but, after 32nm, maybe it's too difficult”, says Saito, “so another way may be necessary.”
The second headache is lithography. “32nm may use modified immersion steppers or EUV”, says Saito, “the big problem is that in EUV there are two groups, one is ASML, the other is Nikon and Canon. There are delays in both groups.”
So the the post-32nm prognosis may not be so good.
“If the lithography and the floating gate are limited”, concludes Saito, “then we're stuck.”
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