Toshiba is spending its R&D dollars on technologies that will take it beyond floating gate flash, as is shown by the announcement of a trapped charge flash structure which would be suitable for a 10nm semiconductor process.
Toshiba's double tunneling layer technology for a SONOS (Silicon Oxide Nitride Oxide Semiconductor) type of flash memory would deliver a 100Gbit density device.
Toshiba is, presumably, putting its development money into trapped charge (often called MNOS technology) of the type being developed by Saifun and Spansion, because it is concerned about the future scalability of traditional floating point flash technology.
A couple of months ago, the CEO of Toshiba Semiconductor, Shozo Saito, told me: "At this moment we're feeling good about the extension of 43nm to 32nm. We start 43nm at the beginning of next year, and we have a good feasibility study of 32nm for 2009. The problem is that, after 32nm, we have some headaches."
The first of these headaches is the floating gate structure itself. "At the moment the structure is floating gate but, after 32nm, maybe it's too difficult", said Saito, "so another way may be necessary."
The double tunneling layer technology for a SONOS structure may be that other way. The structure sandwiches a 1.2 nm silicon nanocrystals layer between 1nm thickness oxide films, using the natural characteristic that resistance changes with changes in gate voltage.
Using thinner tunnel layers than early version SONOS element tunnel layers, makes it easier to migrate to advanced devices with finer lithography.
Toshiba says it increased the amount of saved electrons by changing the nitride film from Si3N4 to Si9N1.
TOMORROW: TEN BEST WOMEN IT SCIENTISTS
Leave a comment