Mannerisms

“There’s been a 40 per cent decline in the last four years in design starts for ASSP/ASIC”, says Moshe Gavrielow, the new CEO of Xilinx.

The rate of decline of new ASIC designs is so fast that, according to the CEO of eASIC, Ronnie Vashista, on present trends, there will be only 250 ASIC design starts in 2030.

“More than 50 per cent of ASICs require at least one re-spin,” says Gary Myers, CEO of Synplicity.

EDA tools are about to break down, according to Wally Rhines, CEO of leading EDA tools supplier Mentor Graphics. “What is the next thing to break down?” His answer? “There’s one out and out winner, place and route.”

The EDA industry’s business model is broken, says Jack Harding, CEO of eSilicon.

“In the EDA industry they sell the tools to the customer and, if the chip doesn’t work, the EDA companies still get paid”, says Harding, “the EDA industry is not sharing the risk of development. There’s a fundamental disconnect in their business model, which is why they’re having difficulty as an industry right now.”

Of course all this industry breast beating is not totally without commercial calculation.

Gavrielow is promoting FPGAs as an alternative to ASIC/ASSP;

Vashista is promoting the direct write e-beam approach to ASIC manufacturing;

Myers is promoting his FPGA verification and prototyping tools;

Harding is promoting his risk-sharing business model;

Rhines reckons he’s got the one and only answer to the impending breakdown in place and route tools;

Everyone’s very outspoken about the industry’s failings when they’re talking up their own book.