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TSMC To Start Risk Production On 32nm Next Year

TSMC, the Taiwan foundry, will be in risk production of 32nm wafers in Q4 2009, according to Tom Quan, deputy director, EDA & design service marketing programme at TSMC.

 

This week Quan presented TSMC's  Unified Design For Manufacturing (UDFM) architecture. aimed at 32nm processes and below.

 "We have a number of customers planning their road map, and we need to have the architecture today so they can start planning their products," said Quan.

 

"The key thing in delivering 32nm is accuracy", added Quan, "we need to deliver an accurate model of what the process looks like to a designer. DFM (design for manufacture) depends on providing accurate information to the designer."

 

"What we're doing for 32nm, as DFM becomes more and more important, is to introduce a new architecture which delivers more information to the customer. So we're delivering to the customer, the original engine which generates the data."

 

This is a risky move for TSMCD because it gives customers, and possibly rivals, an unprecedented level of detailed  factory data about its processes.

 

So why do it? "Because it delivers a large amount of very accurate data to the customer early", replied Quan.

 

How's 32nm coming along? "We've been running test-chips", said Quan. The intention is to have commercial wafers selling for profit out of the door by the end of next year.

 

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