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Why Can't Intel Do Low-Power?

Why can't Intel do low-power? Simple answer: Intel has always scaled for speed. Does that mean Intel can't or won't scale for low-power when low-power is required? Yes, seems to be the amazing answer.

 

Nine years ago, Andy Grove, then Chairman of Intel, came to London and announced that Intel had spent $4 billion acquiring communications companies like Level One, Softcom and others, and had changed the Intel mission statement to become the 'building block supplier to the Internet economy' from the old mission statement which was to be 'the building block supplier to the new computer industry'.

 

Over the years 'Internet' increasingly came to include 'mobile Internet'. But still Intel continued to scale for speed. In 1997, Intel acquired an ARM architecture licence when it bought part of DEC.

 

Intel used the ARM licence to make chips it called X-Scale, but Intel still scaled for speed, and marketed  X-Scale processors not on their power efficiency but simply on their MHz.

 

It beggars belief that some bright spark at Intel didn't say: 'Shouldn't we be developing low-power processors for mobile applications?' But, if  some bright spark did, the bright spark was, apparently, ignored. Intel kept on scaling for speed.

 

"We are one or two orders of magnitude better on passive power than Intel", says Ian Drew, vice president of marketing at ARM, "we expect an ARM processor to last multiple weeks in standby mode, not days or hours. If you leave a laptop on standby overnight it will drain the battery but if you leave a Smartphone on you expect it to last days."

 

Texas Instruments' ARM-based OMAP processors draws about a Watt of power, about five times less than Intel's Atom. TI points out it's the difference between a battery lasting a day or not lasting a morning.


At Computex, Nvidia demo-ed an ARM-based device giving 26 hours of video playback on one charge, while Intel showed Atom-based machines with four to six hours battery life.

 

Although Intel is hoping to cut power down in its next generation of Atom, that is two years away. And by that time, ARM will have moved on.

 

"There tends to be a 50 per cent improvement in power efficiency at each new generation of ARM," says Warren East, CEO of ARM.

 

It is a lucky break  for ARM, now that Intel is feeling obliged (once again) to compete in the mobile space, that Intel, despite its $30 billion + of annual revenues, hasn't applied sufficient resources  to developing low-power chips. 

 

"How incredibly fortunate it is", says East, "that Intel has done a job that we would consider not a very good job on that."

 

"Even if they (Intel) have another order of magnitude reduction, they're still not in the ballpark of where they need to go," says Greg Delagi, TI's wireless boss

 

 So the extraordinary question remains: Why, after all these years of aspiring to be a telecoms player, is Intel still incapable of doing low-power?

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Comments (4)

Chintan:

Hi,
Nice roundup, could you personally answer the last question..
"Why, after all these years of aspiring to be a telecoms player, is Intel still incapable of doing low-power?"

Regards,
Chintan

David Manners Author Profile Page:

Now you've put me on the spot.
Personally, I think Intel's top management try to get into new market areas without doing the work involved to assess what those markets require.
e.g in their (last) ASIC diversification Intel said the ASIC division couldn't use Intel's EDA tools or fabs
& in their (previous) mobile chip diversification Intel top management said the mobile chip division couldn't use Intel's latest processes.
Now, in their latest move into mobile chips Intel is, apparently, telling its people to try and sell chips which have vastly inferior power characteristics compared to rivals chips.
So I would answer the question by saying there appears to be a massive dislocation between Intel's top management and its engineers.

Peter B:

Surely this is a combination of hubris and the usual large company effect. I recall interviewing a potential hiree from Intel, who talked about a x86 processor design, where his group was working on one part (the floating-point unit, I think), whose physical location in the die had been assigned early on in a big meeting. They were having trouble getting the signals to and from another unit fast enough, but the solution of reshuffling the upper-level die layout, which seemed obvious to me from what he said, was just not seen as possible. I wonder if this was the famous case where the FP unit miscalculated a weird variety of operations, and Andy Grove (who had once rejected a short paper of mine on the basis that IBM's numbers for the avalanche breakdown-controlling coefficients seemed good enough for him) ignored IBM's data on the errors.

david manners:

Thanks Peter, fascinating stuff

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