8 bit-per-cell Spansion Memory For Cheap Content Delivery

Using the  trapped charge technology which it got from Saifun, now a Spansion subsidiary, Spansion has decided not to follow the obvious route of developing leading edge memory with a standard number of programme/erase cycles, but to stick with the limited cycle capability of high bit-per-cell technologies, and increase packing density per sq mm to minimise die size..

"We tell Saifun: 'Don't worry about increasing the number of cycles but increase the packing density'," says Bertrand Cambou, CEO of Spansion.

So Saifun is working towards six bit-per-cell and eight bit-per-cell flash memory and not bothering about the restricted cycle which, in the Quadbit four bit-per-cell chips Spansion is currently selling, about to only ten programme/erase cycles.

The rest of the strategy is to use the 4, 6 and 8 bit-per-cell technologies to produce very small die

The application for these small die, high bit-per-cell memories is content delivery e.g. music sold on a card.

 "Content delivery is all about very low-cost solutions which means very small die sizes," said John Nation, director of corporate marketing at Spansion.

So the trick is not to waste transistors, but to develop chips with densities which fit the applications as precisely as possible.

Spansion is making Quadbit chips in densities of between 256Mbit and 2Gbit.

Quadbit is currently being made by Spansion on 65nm processes, but Quadbit chips will be moved onto a 45nm process next year.