Mannerisms

Good to see my source was right about UMB... :) (http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2008/09/why-does-qualcomm-keep-losing.html)

BTW, one small factor going against Qualcomm that is unfolding as we speak: looks like their focus on 45nm has made them late (or non-existent?) on 40nm. Point in case: Snapdragon2, which is a large and digital-centric 45nm chip sampling in 2H09. Quite a few competitors will be sampling 40nm chips even before then...

In fact, I'm starting to wonder - might Icera beat not just ST-NXP and Infineon to 40nm (see http://www.eetimes.eu/210603903), but also Qualcomm? I'm obviously thinking here that my Mid-2010 estimate might have been too conservative and we might see it sampling in, say, 2H09... :)

Now that would be a thing. I will try and find out when Icera will have a 40nm chip.
I noticed that earlier today TSMC announced volume production on 40nm for AMD, NVidia and Altera so it's on the cards.

I did the unthinkable and Googled for 'icera 40nm', and look what I found: http://fplreflib.findlay.co.uk/articles/15631/What%20Flavour.pdf (read the second to last paragraph)

Broadcom won't tape-out anything on 40 before next year, Infineon always lag behind, and most companies including Qualcomm would likely need a respin anyway (unlike Icera) and might be more delayed by certification times because they're not software-based. So given all that, it seems nearly inevitable to me that Icera will be sampling the first 40nm merchant baseband (!!!) if everything goes well and as planned.

Of course you could argue '40' is a bit random and IDMs like TI might be competitive even on '45' (in TI's specific case I'm pretty sure they aren't for gate density though), but it'd still be a very impressive achievement.

Well Icera say that this comment came out of a TSMC conference in September when a TSMC guy said that Icera would be the first companuy In Europe to tape out on 40nm.
But Icera tell me that they're not taping out on 40nm this year, and won't say when they will tape out on 40nm, but confirm that the design they are currently working on is a 40nm design.
That doesn't take us much further.
I see that the first people to use TSMC's 40nm process are Altera, NVidia and AMD which means they'll be using the high performance version of the 40nm process.
I don't know if the low-power version of the 40nm process, which is the one Qualcomm and Icera will be using, is ready yet.

Very interesting, cheers - of course that gets us back to square one, ah well! :) Apparently both 40G and 40LP are qualified, while "TSMC’s roadmap includes an LPG technology that improves the performance of the 40LP process, according to Ma."

My understanding is that Altera's FPGAs used triple-oxide so they're 40LPG; therefore I'm a bit confused by this. Maybe Altera didn't begin production yet but still is the first on 40LPG? Or maybe the above statement is simply wrong...

I've actually been suspecting that Icera's 40nm chip would be based on 40LPG since one of their presentations claimed they saw a 'limited call for LSTP processes' (i.e. ultra-low-leakage) but at the same time higher-leakage gates were much better for active power consumption and perf/mm² (especially for a programmable solution!) - So even if 40LP was ready maybe that's not what we should be looking at.

You're well ahead of me, I've only seen fairly bare bones announcements about TSMC's 40nm. Thanks for flagging up what an interesting series of scenarios it could produce. Now I'll be watching this with interest.