IMEC has done something pretty amazing in fabricating III-V structures on silicon wafers.
The problem with III-V wafers is that they are expensive and small.
If chips can be made which exploit the higher electron mobility of III-V while being made on standard, comparatively low-cost, large silicon wafers - then the semiconductor industry has a powerful tool boosting the performance of ICs, and consequently of all electronics products, without a large cost increase.
So the IMEC achievement has big implications.
What IMEC has done is to grow indium phosphide layers on silicon wafers and show the way to using other III-V compounds, like gallium arsenide, on silicon.
The technique also enables the integration of opoelectronic devices on silicon ICs via a selective area growth of III-V materials on dedicated silicon areas.
'This result,' says IMEC, 'is a major step forward towards the fabrication of high-performance Ge/III-V CMOS devices and the integration of optoelectronic devices on silicon ICs.'
P.S. Mike Bryant kindly tells me I have missed the main point here which is that this achievement by IMEC allows the fabrication of a viable mass-producible N transistor for use in a CMOS gate at the 16nm node. Now, thanks to IMEC, there is one. So thanks Mike.
David - sorry to say but IMEC wasn't first. The DARPA COSMOS project(s) Compound Semiconductor Materials on Silicon spawned the first monolithic integration of III-V structures and CMOS on silicon in 2008. The CMOS was UK however, the III-V growth and interconnect was US.
Mike is correct, the European effort is for the extension of digital logic. The DARPA goal is to create high performance, high speed mixed signal.
Thanks jamo, interesting.