"Intel was supposed to have 22nm at the end of this year or Q1 2012. Now this has been moved forward to sometime in 2012," says Professor Asen Asenov of
"Everyone is very curious that there is no IEDM paper from Intel about Intel using 22nm finfets," Asenov tells me.
Usually if Intel is introducing a new technology in the year ahead, they have a paper on it at IEDM but, although Intel has a paper on compound finfets made on an InGaAs process at this week's IEDM, it does not have a paper on 22nm finfets made on a conventional CMOS process which Intel says will be the process used for its 22nm finfet production.
Although the finfets to be introduced by Intel are to be built on a conventional CMOS silicon substrate, Asenov's group at
"Intel has chosen bulk because it is the cheaper option, but it has a lot of problems in terms of manufacturability and control," says Asenov.
Asenov reckons that finfets built on an SOI substrate could have significant advantages in terms of simpler processing, better process control and reduced statistical variability.
His group has shown that SOI finfets will meet the low statistical variability requirements of 11nm CMOS technology.
That means SOI finfets will be useful for three generations of process technology justifying the expense that will be incurred in moving to new transistor architecture.
"When you introduce a new device architecture you hope this will allow you to scale for several process generations - if it looks like it will only scale for one generation, it is not a good investment," says Asenov, "we have shown we can scale SOI finfet for three generations - 22nm, 16nm and 11nm."
Asked if there was any difference between what Intel calls a 'trigate' transistor and what the rest of the world calls a finfet transistor, Asenov replies: "Not a lot really. Trigate is a specific implementation of finfets. They use the word trigate as a differentiator."
Asked if there were significant differences between finfet transistors and fully depleted SOI transistors - the two main contenders to be the next mainstream IC transistor, Asenov replies: "Fully depleted SOI has very similar advantages to finfets."
Told you so in a previous comment. To have Intel screw up a process will be a first, but I am expecting it.
the "Intel process advantage" ... the "Intel process advantage" .... written everywhere .... just too much presure ... they drop SOI just because it was the IBM and AMD choice for long .... so technical choice for bad reason.
- to release a new process just to keep the Intel traditional rate of process introduction ... despite the fact that this process is not ready
- to avoid SOI, the easiest route (no dopant, so no dopant variation !), just because it would give some credibility to competitors technicals choice ....
In the meantime, they screw up on the design big time:
- itanic (it sink, isn't it ?)
- Atom (it bomb isn't it ?)
- Larabee (Lara ... what ?)
Remember (and repeat after me) ... Empire do not last for ever ... Empire do not last for ever ... lack of humility and fresh thinking will be Intel doom ...
I understand, fabrice, that it is easier to make finfests on an SOI process but you're still stuck with the extra cost of the wafers.
The wafer cost more, but you skip some process steps, so SOI proponent that SOI cost is in par with Bulk, when you count the whole manufacturing cost (something which was not true before).
For me the bargain is that with SOI you buy a solution to a problem which is completely unsolved otherwise (dopant flucatuation) ... and personnaly I dont see any kind of solution to this problem ? (when you have so much little dopping atom, the distribution is discrete, no more a nice percentage of the matter), just mother nature speaking here.
When I see the whole hollyhood show about 3D finfet (excuse me TRIGATE !!! (R) (c) ), I start to think that Intel will screw up this node. Just because it is not the way things have to be done.
Marketing is cleary taking over at Intel, without any limits ... I thinks Intel is at a stage where they are ready to hire ED like manager ;)
Excellent point, fabrice, and let's hope the Evil Empire sinks in a sea of SOI.
LOW-K ,GATE -FIRST, CELL BE ,PPC
IBM Semiconductor has to die,32NM process yields surprising
@ IBM BEST: & your point is?
@ IBM BEST: surprisingly good or surprisingly bad?
I think people need to remember it is Intel and not IBM or others that is the IC manufacturer on the EC's SOI450 project. Intel always makes sure it covers all of the bases and if SOI becomes cheaper they will change over in a shot. Unfortunately at the moment the cost of the extra processing at 22nm is roughly half of the cost of the extra wafer cost. But at 15nm or 11nm this may change, we will have to wait and see.
You can be sure Intel makes its decisions on pure profit grounds and not on sentiment for any past actions or competition. Is this enough to keep the empire going, again we will have to see.
That said, if Intel did want to switch, SOITEC could not currently deliver anything like the number of wafers Intel would need if they did and that issue has to be taken into account as well.
As for Fabrice's listr of 'failed' designs mentioned, Itanium is a HP special, Larabee has morphed into Knight's Corner so we have to wait and see if it will succeed or not, whilst Atom has been a massive success despite Intel's own management's scepticism.
And will everyone kindly go and do just a little bit of reading of tech papers and see that basic FinFets and Intel's Trigate are not the same !
So can someone who understands these things tell me who is right?
Mike Bryant: "basic FinFets and Intel's Trigate are not the same!"
Asen Asenov: "Trigate is a specific implementation of finfets. They use the word trigate as a differentiator."
They can both be true, but only if we split hairs.
Hi Stooriefit
I have sent a slide to David Manners showing the differences between the 3D options. I assume he can see your e-mail address so can send it to you.
As you will see it's not so much about splitting hairs as removing some of the nitride layer on top of the channel.
Anybody else who wants a copy please ask DM as well.
Mike
Can I pls have a copy of the difference bt fingers and intels trigate? Thank you.
I've emailed it over, Brian. Anyone else who'd like a copy of Mike's picture of the difference between a finfet and an Intel Tri-Gate please send their email address to me at david.manners@rbi.co.uk
I've forwarded Mike's picture to you, Stooriefit. Anyone else who'd like it please send me your email address to david.manners@rbi.co.uk
David, do you have a Twitter account? I wanted to (re?)tweet this (great article and excellent discussion, folks!). Or should I just cite Elec Wkly? thx.
I'm afraid I don't have a Twitter account, Adele. Please disseminate the piece any way you wish - so long as you give us credit.
As an aside, all FinFETs and Trigate are just more flavors of MuGFETS (multi-gate FETs), first proposed by one of the giants of the research community -- Jean Pierre Colinge -- many years ago. He first proposed them on SOI. And in an interesting twist of fate, JP will get the 2012 IEEE Grove Award for his SOI work....