Intel’s poor timing on 45nm release

When it comes to public relations, you’d think Intel would have a learnt a thing or two over the past few decades. Though not, it would seem, about timing. Late on Friday (actually Saturday in the UK), when all self-respecting journalists were down the pub, the chip behemoth released details of its 45nm process for the next generation of microprocessors. This isn’t some thrupenny-bit, “we punt these out every day” type release – this is one of Intel’s biggest press events of the year. penryn.jpgAnyway, it seems the Penryn processor will use a high-k gate dielectric based on Hafnium and metal gates for transistors, although the latter will differ for NMOS and PMOS transistors. The combination offers 20% more drive current, or one-fifth of the source drain leakage, or a tenth of the gate leakage. Lithography remains at 193nm, and Intel will not be using immersion, it said. To read some of those tedious facts about how many billions of transistors fit aongside the angels dancing on a pin, see Intel’s Fun Facts pdf. (I kid you not) There’s loads more proper detail on the release from these quality sites: The Register: Intel 45nm CPUs to use metal gates, high-k dielectric ZDnet: Intel shows off Penryn chips The Inquirer: Intel does High-K and metal gates EETimes: Intel tips high-k, metal gates for 45-nm

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