One for SOC designers. Check out a new in-depth feature that has just been posted on Electronics Weekly.com - Traffic management: A growing nightmare for SOC designers
It starts with the premise that SOCs (systems on chips) are outgrowing centralised-bus-based architectures and that accurate use models are vital to understanding traffic patterns. According to the author, Ron WIlson, a combination of ESL (electronic-system-level) and cycle-accurate approaches is necessary to understand interconnects. Indeed as SOCs evolve, interconnect modeling will become mandatory...
"The SOC (system on chip) began life in the image of the board-level computers that preceded it: as a central processor that a CPU bus connected to local memory and peripheral controllers. That CPU-centric, bus-oriented architecture has since been the underlying plan for many SOCs.
But integration has brought complexity in the form of complex peripherals with their own DMA (direct-memory-access) controllers, coprocessors, and additional central processors, all on the same die.
Accordingly, the interconnect architecture of SOCs is changing. The old CPU-centric bus is fast retreating to within the functional blocks of the chip; multiple buses, specialized point-to-point links, and on-chip networks are replacing it." it begins.
