Check out an interesting feature article we have just uploaded, regarding FPGA designs - Debugging FPGA designs harder than you think
The main points to note are:
The main points to note are:
- Issues that arise during FPGA debugging include the quality of RTL (register-transfer-level) code, the quality of the IP (intellectual property), the quality of results from the synthesis engine, and the quality of results from the place-and-route engines.
- It's common in FPGA IP to use two representations - one for high-level simulation and the other for the actual implementation.
- IP models you use for simulation may differ in significant ways from the corresponding models the place-and-route software uses.
The article begins:
In the not-so-distant past, the question used to be, "Can you do that task in an FPGA?" With the advent of modern FPGA devices, however, the question has become, "Why wouldn't you use an FPGA?"Read the full article >>
