Just a quick post to flag an interesting article on the site that has proved very popular over the last few days.
Through-silicon via (TSV) on chip interconnection of memory, processor and sensor elements looks the most likely route for 3D chip design, writes Richard Wilson.
He begins:
He begins:
As the complexity of system-on-chip semiconductor devices grows designers are exploring the practicality of so-called 3D chips.
3D chips can take many forms but the most practical would seem to be through-silicon via (TSV) technology which allows die to be stacked on top of one another.
A common element of all processor-based systems is memory and Samsung Electronics and Micron Technology are proposing an open interface specification for TSV-based memory technology called the Hybrid Memory Cube (HMC).
Details of HMC technology are vague, but it uses a stack of TSV-bonded DRAM die with the potential for higher memory density and data paths.Read the full article >>
The companies claim a x15 improvement in density over traditional DDR3 DRAM devices.
"This collaborative is an accelerator for highly promising technology that will benefit the entire industry," said Jim Elliott, v-p memory marketing at Samsung Semiconductor.
"HMC is unlike anything currently on the radar," said Robert Feurle, Micron's v-p for DRAM marketing.
Samsung has already demonstrated how TSVs and 3D packaging can reduce power consumption in 32Gbyte DDR3 registered DIMMs.
"TSV allows us to stack dies onto one another and therefore increase the density of any given package," Samsung spokeswoman Ujeong Jahnke told Electronics Weekly. "The RDIMM is manufactured by stacking 4Gbit DRAM die."
