Core Values

How's your IP buying experience? If you are like most people I've talked with it ranks somewhere between a visit to the dentist and buying a used car.

At the IP-SOC 2006 conference this year in Grenoble, Gartner's Jim Tully called on the IP industry do a better job of conveying the true value that they provide to customers and at the same time to think about more transparency in pricing to improve the buying experience among customers. That's a lovely thought, but is there a precedent for such move?

Recall in the early 1990's, General Motors was losing market share and though they knew many of the issues that irritated the customers, their biggest problem was getting their established divisions to address them. So instead of trying to convince the divisions to fix them, they did something radical and established a new division, Saturn. In trying to learn what kind of product it should build, Saturn conducted a series of focus groups. One unexpected thing stood out--people hated the buying process. They felt that somehow, someway, the sales person would end up taking advantage of them. Rather than feeling happy about the deal, customers would walk away feeling that they had somehow been taken advantage of. They thought 'Gee, if I had just toughed it out for another 3 hours with the creepy sales guy I might have gotten another $500 off, or free floor mats.'

Saturn responded to this with a transparent pricing policy--here's the price, take it or leave it. Everybody pays the same, no matter what dealer you buy it from, no matter which sales guy you get. And customers loved it (aside from the fact they now owned a Saturn.)

So the question is; would such a system work in semiconductor IP. Would it create happier customers and more thriving IP market or would it be a race to the bottom for all concerned?

I think not. The Saturn experiment worked primarily because Saturn had a monopoly on Saturns and ensured that they could never be a price war across dealers. Saturn competed against Honda, which could set their price on par with Saturn and change the discussion to 'OK, we're the same price, now let's talk about quality.' So what Saturn effectively did was to change the discussion from price to value, which was a very good thing. (Fortunately for Saturn, it was also known for its excellent quality.)

Perhaps that's the real lesson of Mr. Tully's advice. If customers are making their buying decision purely on price, they are losing sight of the fundamental reasons that we have an IP industry--to create an efficient semiconductor industry that leverages and rewards the hard work of others to drive us forward. Leaders will ensure they have a fair exchange of price for value in the goods they transact. Losing companies will focus on price, inevitably temporarily.

If you have an opinion about this, please feel free to post it here, or email me in confidence at core.values@ip-extreme.com

I'm excited as anyone about System Verilog. It is a significant step forward towards a unified implementation and verification language for the design of semiconductors. Yet the reality of it supplanting today's languages is still far away due to uneven support by the EDA community.

In the article "System Verilog support for design falls short", Richard Goehring reports that designers are not rushing to the new language as fast as anticipated and cites very uneven support of System Verilog features by the EDA community.

Customers are further complaining about the lack of uniform industry support of the language in John Cooley's DeepChip newsletter. They hint of the risk of using System Verilog will lock them into a specific company's EDA design flow because they might use a feature that is not yet implemented in a competitor's product.

That's a big problem for IP companies to adopt it as a standard language. IP has an incredibly long shelf life and therefore needs to be built to last and be immune to the twists and turns of ever changing EDA flows and design methodologies. This means IP needs to be built on well-established languages and tools.

Perhaps the most obvious (and therefore least likely) solution for this System Verilog situation is to eliminate all "optional features" from the language. Tools would support the full language or not. This would also eliminate the need for meaningless spin-doctoring such as "we support most of the features", "we support 95% of the features", "we support all required features", etc.

Lacking that, it looks like we have no alternative but to stick with the old standbys of Verilog/VHDL on the design side and the alphabet soup of proprietary verification languages that can run on industry standard simulators via PLI connections.

FPGA companies are dutifully keeping pace with Moore's Law. Every year, we get faster, larger devices and the pundits regularly predict FPGA's are nearing the point where they can steal market share from ASIC and ASSP companies. But it never happens. ASIC starts continue to drop, but it is the ASSP companies that seem to be benefiting from that market shift. Isn't that curious?

Consider a few insightful words from Lewis Carroll's Through the Looking Glass.

"Well, in our country," said Alice, still panting a little, "you'd generally get to somewhere else -- if you run very fast for a long time, as we've been doing."

"A slow sort of country!" said the Queen. "Now, here, you see, it takes all the running you can do, to keep in the same place. If you want to get somewhere else, you must run at least twice as fast as that!"

The Queen is right: keeping up with Moore's Law gets you exactly where you are today. The fundamental problem lies with the growing need for IP, so completely vital to any serious design today. And not only is the number of IP instances per device growing, but also the size of each IP. Gains in device capacity are quickly consumed by the increased needs of new, higher complexity IP.

I believe the the future offers three scenarios:

• If FPGA's can keep pace with the growth of IP complexity, then the current status quo will be maintained
• If FPGA's can grow faster than IP complexity, there is a real chance to post significant market gains as a viable alternative to ASIC
• If FPGA's grow slower than IP complexity, then FPGA's could be moving towards technical oblivion

So what advice should we give Alice? Run faster.