I'm excited as anyone about System Verilog. It is a significant step forward towards a unified implementation and verification language for the design of semiconductors. Yet the reality of it supplanting today's languages is still far away due to uneven support by the EDA community.
In the article "System Verilog support for design falls short", Richard Goehring reports that designers are not rushing to the new language as fast as anticipated and cites very uneven support of System Verilog features by the EDA community.
Customers are further complaining about the lack of uniform industry support of the language in John Cooley's DeepChip newsletter. They hint of the risk of using System Verilog will lock them into a specific company's EDA design flow because they might use a feature that is not yet implemented in a competitor's product.
That's a big problem for IP companies to adopt it as a standard language. IP has an incredibly long shelf life and therefore needs to be built to last and be immune to the twists and turns of ever changing EDA flows and design methodologies. This means IP needs to be built on well-established languages and tools.
Perhaps the most obvious (and therefore least likely) solution for this System Verilog situation is to eliminate all "optional features" from the language. Tools would support the full language or not. This would also eliminate the need for meaningless spin-doctoring such as "we support most of the features", "we support 95% of the features", "we support all required features", etc.
Lacking that, it looks like we have no alternative but to stick with the old standbys of Verilog/VHDL on the design side and the alphabet soup of proprietary verification languages that can run on industry standard simulators via PLI connections.
