Core Values

On behalf of the IP industry, I’m happy to paraphrase Mark Twain in that the news of our death as been greatly exaggerated.

Mark LaPedus of EETimes last week made a few provocative statements in his column last week Semi IP Sector is a Lost Cause calling the semiconductor IP sector a “non-profit business” and posted a follow-up challenge to companies to challenge his conclusion Letter to Semi IP vendors adding that it would be probably a better use of his time to improve his golf game than to write about the IP market.

As I've written in this column before, a key impediment to System Verilog's application as a IP design language is uniform support across the major EDA players. Without a consistent set of implemented features and tested interoperability, IP design with System Verilog is too risky.

A significant step in System Verilog's maturity happened last week with the announcement that Cadence and Mentor have teamed to work together to develop the Open Verification Methodology around System Verilog. Bravo! With this move, the odds of System Verilog IP working across platform dramatically improve.