As I've written in this column before, a key impediment to System Verilog's application as a IP design language is uniform support across the major EDA players. Without a consistent set of implemented features and tested interoperability, IP design with System Verilog is too risky.
A significant step in System Verilog's maturity happened last week with the announcement that Cadence and Mentor have teamed to work together to develop the Open Verification Methodology around System Verilog. Bravo! With this move, the odds of System Verilog IP working across platform dramatically improve.
Oddly, Synopsys was not invited to the party and was left standing by the wall with a cup of fruit punch and no dance partner.
While a ménage à trios might be infinitely more interesting, perhaps this is the most practical way to make real progress for the industry. It’s difficult enough to have two large companies work together on something strategic for the entire industry, getting three competitors together on the same page is probably more than we can ask for. With solid progress by two, the third will inevitably follow. Let’s hope it’s the right two.
