Low-Power Design

Normally, silicon scaling is a good thing. Except when you are making power devices, as people working in the automotive semiconductor business explained at the Design Automation and Test in Europe (DATE) conference this week in Dresden.

Klaus Meder, president of the automotive electronics division at Robert Bosch, explained in his keynote speech that denser devices are causing headaches when it comes to ensuring the reliability of power semiconductors in cars. He showed heat maps of old versus new parts and how lower silicon area is causing stronger hot spots to build on the devices. This is not good news for an industry that is expecting to put a lot more electronics into cars.

The Texas Instruments MSP430 is practically synonymous with low-power processors and, although the company may not care much for the idea of clones of the architecture appearing, that is being helped by a crop of research processors that explore the limits of the threshold voltage of CMOS transistors.

These designs are helping to push the MSP430 into lower-power territory than even the 'Wolverine' that was first unveiled just over a year ago at the 2011 International Solid State Circuits Conference (ISSCC) and which coupled a 130nm - running with reasonably conventional supply voltages - together with the company's ferroelectric memory technology as a more energy-efficient alternative to flash. The chip was launched by TI as a commercial product earlier today.

Yoichi Yano, executive vice president of Renesas Electronics made energy saving the theme of his keynote at this week's International Solid State Circuits Conference, describing some of the techniques the company is putting into action to make silicon suitable for self-powered sensor nodes.

The International Solid State Circuits Conference kicks off next week and Texas Instruments, which unveiled a low-energy digital signal processor last year based on near-threshold logic circuitry, is keen to tout its involvement in more low-power work this year.

The electronic edition of the winter issue of Chip Design magazine contains a round table discussion about rapid prototyping and the interview wastes no time in asking about the technique's role in low-power design, which is not quite a direct one yet.

It's no secret that the clock speeds of processors have hit a glass ceiling. But until the latest iteration of the International Technology Roadmap for Semiconductors, we still expected them to increase by close to 10 per cent a year. Not anymore. The slow rise has been replaced by a crawl that acknowledges the need to keep both cost and power consumption under control.

The 2011 International Technology Roadmap for Semiconductors (ITRS), finalised late last year, has been publicly released.

The roadmap looks at the problems facing the chipmaking industry from now until 2026 and includes some updates that focus on low-power design. The slides prepared by Andrew Kahng on design, for example, show how expectations on power have changed - and in a quite a big way since the last update.

EETimes has put a video on YouTube that shows short excerpts from the keynote given by HP Labs' Prith Banerjee at the recent DesignCon in California where he talks about the work being done there to use optical interconnect to take backplane speeds from 10 to 300GB/s and higher and drop their power consumption.

Low-Power Engineering has posted the last instalment of its round-table interviews on making software more energy efficient and some of the problems that face an industry that needs to expose low-level hardware details through a compiler-insulated interface.

Power consumption is hard to predict even with a reasonable amount of architectural information and that is underlined in a paper that appeared at the Architectural Support for Programming Languages and Operating Systems (ASPLOS) conference last April. but recently picked up by LinuxDevices. In the paper, the researchers argue that processor maker need to make power information for their products more readily available to software developers.

Carbon Design Systems has produced a site that makes it possible to download transaction-level models for use in system-level simulation to let designers see how IP cores will perform, and potentially feed into high-level power analysis using, as John Blyler notes in his blog, sites such as ChipEstimate.

Transaction-level modelling and system-level analysis are important tasks for any low-power design activity given the major savings that can be made at this level: simply stopping transactions from repeating needlessly pays big in terms of reducing circuit activity and, with it, energy usage.

So, a new release in the SystemC world is something to watch and version 2.3 of the library is the first to make its way towards public access since the merger of Accellera and the Open SystemC Initiative (OSCI). Accellera has put up an early version of the v2.3 library for public review to work out whether some of it needs to change to work with the latest version of the language standard - IEEE 1666-2011 - to be published this month:

It's the season for predictions and Brian Bailey, writing at EDN points out some power-related issues among other predictions made by some of the people he asked.

Magnetic memory (MRAM) was not at my list of candidates for future cache memories but in a paper for the latest issue of IEEE Transactions on VLSI Systems, a group of engineers from Xi'an Jiaotong University make the case for using the memory to replace SRAM in level-one (L1) caches despite a very obvious drawback: the write speed and power consumption of MRAM are not good at all.

Hongbin Sun and colleagues focus their attention on the more recently variant of MRAM, spin-torque transfer (STT) rather than traditional MRAM, which does not scale so well with process. After all, it's going to take a while for MRAM to become a serious candidate for cache memory in mainstream SoCs. However, STT has some crossover with memristor technologies and seems to have potential beyond 28nm or 22nm.

Linus Torvalds has signed off on the latest release of the Linux kernel, version 3.2, and it contains several additions aimed at power-management. The new code modules have been submitted over the past year by engineers working at Samsung and Texas Instruments, among others.

Linux 3.1, completed late last year, also included some tools for power monitoring: cpupowerutils. The latest batch of additions focus on ways to improve how the kernel deals with systems that use dynamic voltage and frequency scaling (DVFS), extending power management to more devices in the system than just the CPU.

When looking at new architectures for low-power operation, it is easy to get fixated on one part of the design and ignore the ramifications for the rest of the system. The consequences of that are demonstrated in a paper that was presented at last year's International Symposium on Low-Power Electronic Design in Japan.

Rami Abdallah, Pradeep Shenoy, Naresh Shanbhag and Philip Krein from the University of Illinois at Urbana-Champaign looked at how dynamic voltage scaling affects not just processors and logic but the DC/DC converter used to supply power to the circuitry, and found that the minimum energy point is not where you expect to find it.

Field-programmable gate arrays (FPGAs) are notorious for high power consumption. They are hard to power down in the same way as custom logic - so they have considerable static power consumption - and they use a lot more gates to achieve the same job with their greater flexibility.

However, a good proportion of an FPGA's power consumption is avoidable. A 2007 study carried out by researchers at the University of British Columbia and published in IEEE Transactions on VLSI Systems found that up to three quarters of the dynamic power consumption could be ascribed to glitches rather than actual functional state transitions for some types of circuit.

With its Consumer Electronics Show in Las Vegas looming, the Consumer Electronics Association has published figures claiming that electronic devices still account for a relatively small share of the electricity consumption in the average US home. Or at least they did in 2010.

The figures were put together by the Fraunhofer Center for Sustainable Energy Systems based on data collected during 2010. The study found that consumer electronics accounted for about 13 per cent of a US home's electricity usage, despite there being around 25 active devices in the average household.

In an opinion piece for Electronics Weekly, head of Nujira Tim Haynes writes that the launch of LTE has met with some power problems. As such, it has not been all that different to that of 3G some ten years. Then as now, power was a major concern as handset designers had not optimised their products and were also waiting on improved digital technology to deliver more efficient signal processing.

This time, although the digital section has once again leapt in complexity, one of the culprits behind the increased power consumption is the power section. As the developer of an envelope-tracking technology, Haynes naturally sees this as one solution to the problem and recovering some of the efficiency lost in the move from narrowband to broadband power amplifiers.

At his View from the Top blog, Achim Nohl writes about the longstanding problem of software failing to take advantage of the power-saving facilities offered by hardware, if not subverting them entirely.

The key in his view, and it's hard to disagree lies in providing better information on power consumption to the software engineers as they write, test and debug code: "The underlying execution target needs to expose the energy consumed by the different components that make up the system - over time and ideally through the perspective of software activity." It sounds easy enough but...