One of the ways to reduce power consumption in processor subsystems is to cut the amount of energy that it takes to shovel data from memory into the processor. The parasitic capacitance and inductance of high-speed buses contribute a lot to the overall power budget for accesses that need to bypass the on-chip caches. If you move the memory devices much closer to the processor, you can cut those parasitics dramatically.
The trick is coming up with reliable designs for 3D stacked processor and memory modules. The work that packaging company Tezzaron is performing with some of its partners can provide a lot of clues as to how the design and assembly process can work. In a two-part guide at EDA Designline, Robert Patti shows the company's current thinking in terms of design flow and uses some tools that are not yet 3D aware, which adds some degree of complexity to the process.
The demonstrator for the flow is a stack involving an ARM Cortex-A processor that is itself split into two parts and stacked, an FPGA die and a DRAM memory stack, all assembled onto an active silicon circuit board acting as an interposer. This is arguably a lot more complex than most likely attempts at 3D design in the near future but allows the team to work out how to partition logic across dice and perform power, thermal and reliability analyses for the resulting stacks.
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