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The Texas Instruments MSP430 is practically synonymous with low-power processors and, although the company may not care much for the idea of clones of the architecture appearing, that is being helped by a crop of research processors that explore the limits of the threshold voltage of CMOS transistors.

These designs are helping to push the MSP430 into lower-power territory than even the 'Wolverine' that was first unveiled just over a year ago at the 2011 International Solid State Circuits Conference (ISSCC) and which coupled a 130nm - running with reasonably conventional supply voltages - together with the company's ferroelectric memory technology as a more energy-efficient alternative to flash. The chip was launched by TI as a commercial product earlier today.

Yoichi Yano, executive vice president of Renesas Electronics made energy saving the theme of his keynote at this week's International Solid State Circuits Conference, describing some of the techniques the company is putting into action to make silicon suitable for self-powered sensor nodes.

The International Solid State Circuits Conference kicks off next week and Texas Instruments, which unveiled a low-energy digital signal processor last year based on near-threshold logic circuitry, is keen to tout its involvement in more low-power work this year.

Magnetic memory (MRAM) was not at my list of candidates for future cache memories but in a paper for the latest issue of IEEE Transactions on VLSI Systems, a group of engineers from Xi'an Jiaotong University make the case for using the memory to replace SRAM in level-one (L1) caches despite a very obvious drawback: the write speed and power consumption of MRAM are not good at all.

Hongbin Sun and colleagues focus their attention on the more recently variant of MRAM, spin-torque transfer (STT) rather than traditional MRAM, which does not scale so well with process. After all, it's going to take a while for MRAM to become a serious candidate for cache memory in mainstream SoCs. However, STT has some crossover with memristor technologies and seems to have potential beyond 28nm or 22nm.

When looking at new architectures for low-power operation, it is easy to get fixated on one part of the design and ignore the ramifications for the rest of the system. The consequences of that are demonstrated in a paper that was presented at last year's International Symposium on Low-Power Electronic Design in Japan.

Rami Abdallah, Pradeep Shenoy, Naresh Shanbhag and Philip Krein from the University of Illinois at Urbana-Champaign looked at how dynamic voltage scaling affects not just processors and logic but the DC/DC converter used to supply power to the circuitry, and found that the minimum energy point is not where you expect to find it.

Field-programmable gate arrays (FPGAs) are notorious for high power consumption. They are hard to power down in the same way as custom logic - so they have considerable static power consumption - and they use a lot more gates to achieve the same job with their greater flexibility.

However, a good proportion of an FPGA's power consumption is avoidable. A 2007 study carried out by researchers at the University of British Columbia and published in IEEE Transactions on VLSI Systems found that up to three quarters of the dynamic power consumption could be ascribed to glitches rather than actual functional state transitions for some types of circuit.

In an opinion piece for Electronics Weekly, head of Nujira Tim Haynes writes that the launch of LTE has met with some power problems. As such, it has not been all that different to that of 3G some ten years. Then as now, power was a major concern as handset designers had not optimised their products and were also waiting on improved digital technology to deliver more efficient signal processing.

This time, although the digital section has once again leapt in complexity, one of the culprits behind the increased power consumption is the power section. As the developer of an envelope-tracking technology, Haynes naturally sees this as one solution to the problem and recovering some of the efficiency lost in the move from narrowband to broadband power amplifiers.

Earlier this year, Abhishek Mahajan and Sorabh Sachdeva of Freescale Semiconductor wrote about the problems caused by temperature inversion in high-Vt cells, a situation where the usual assumptions about heat slowing circuits down fall down. It's time to revisit the subject.

In an invited paper for the International Electron Device Meeting (IEDM) in Washington DC this week, Dennis Buss of Texas Instruments talked about his experience in developing ultra-low power systems, something that he has been specialising in for the past few years.

In an article for Low-Power Engineering, William Ruby, senior director of RTL power product engineering at Apache Design Solutions outlines the top five reasons he has found why customer designs don't go according to plan when it comes to meeting their power budgets.

Some of the items on the list seem obvious, such as an inefficient overall architecture and implementation. But there is detail behind a number of these points that bear closer inspection.

Low-power design and fast testing at the fab are not happy bedfellows. As Giri Podichetty of Mentor Graphics explains at Semiwiki and in a white paper, "the goal of automatic test pattern generation (ATPG) is to achieve maximum coverage with the fewest test patterns. This conflicts with the goals of managing power because during test, the IC is often operated beyond its normal functional modes to get the highest quality test results".

He continues: "When switching activity exceeds a device's power capability during test, it can have detrimental effects on the IC, such as collapse of the power supply, switching noise, and excessive current that could lead to joule heating and connection failure. These effects lead to false failures, and can damage IC in ways that decrease it's lifetime."

In any synchronous system, the clock can consume as much as 40 per cent of chip power. That is not likely to change as more designers attempt to take advantage of the power savings otherwise available by moving to the ultra-low voltage (ULV) or near-threshold voltage regime.

Although we can expect extensive use of clock and power gating in the ULV domain, in any synchronous system the clock is still going to account for the largest single share of the total energy. It is potentially worse as the factors that determine robustness involve some hard tradeoffs against power.

If you're looking for a good introduction on power-aware verification for IC designs, take a look at the tutorial/webinar put together by Gabriel Chidolue, verification technologist at Mentor Graphics.

The leading circuits conferences in 2012 are lining up to have a strong focus on low-power design. February's International Solid State Circuits Conference (ISSCC) has, among other things, a course on low-power analogue signal processing and a forum on power and performance optimisation of many-core processor SoCs - so it spans the gamut of CMOS design.

Semiwiki has kicked off a thread on low-power techniques in use today on chip designs, attempting to find out from users what works and what doesn't. The thread isn't huge right now but people have posted some suggestions, with one of the users providing some tables showing common techniques and their impact on methodologies.

In the days when the mobile phone was used purely for talking to people, the power efficiency of the audio playback was not a huge concern. Unless the circuitry was especially inefficient it would always be dwarfed by the energy needed for the RF subsystem. Now, the phone is more likely to be used as a media player and long-term usage with headphones is a major drain on the battery.

Historically, the Interational Electron Device Meeting (IEDM) has been a forum for chipmakers to unveil their fastest, densest processes. The emphasis has been shifting steadily away from peak speed to more of a tradeoff between power and performance, with several papers reflecting the need to move away from traditional transistor metrics such as current drive.

IBM and STMicroelectronics have recommended, in the past, an approach that looks more at parasitics such as drain-induced barrier lowering (DIBL), as this has a greater effect on performance in all but the fastest, most power-hungry logic circuits. NXP Semiconductor and TSMC worked together in the past decade using simulation to tune devices for real-world circuits rather than ultimate, single-device performance. This kind of work will form the basis of a session at the 2011 IEDM in Washington, DC on circuit and device interaction.

At the Intel Developers Forum, the chip giant's chief Paul Otellini described how work at the company would yield more power-efficient processors, potentially running from solar power.

For a company that is not readily associated with 'low power', Intel is doing what it can to present itself as an alternative to one that is: ARM. However, both are looking at more or less the same option in this case: near-threshold logic. Intel has circuit designers working on designs such as cryptographic processors. ARM is sponsoring research at the Unversity of Michigan, which has academics looking into the practicality of using the logic.

In late August, Freescale Semiconductor, Intel and Marvell Technology were hit by a patent suit by the largely unknown company Power Management Systems, which claimed the three chipmakers infringed on its US patent, number 5,504,909.

The action is potentially troublesome for an industry that has come to rely on power gating as an energy-management technique. The patent does describe, albeit not in much detail, the components for an on-chip power-gating system.

ARM has decided to extend its relationship with the University of Michigan low-power electronics research team that ARM R&D vice president Krisztián Flautner worked with before joining the IP company.

According to Peter Clarke at EETimes: "The five-year, $5 million extension of an existing research partnership will run until 2015 and cover technology for ultra-low energy computing and applications areas including energy-efficient cloud computing; wearable medical and lifestyle devices; energy-efficient trusted computing; and ubiquitous sensor networks."