It's no secret that the clock speeds of processors have hit a glass ceiling. But until the latest iteration of the International Technology Roadmap for Semiconductors, we still expected them to increase by close to 10 per cent a year. Not anymore. The slow rise has been replaced by a crawl that acknowledges the need to keep both cost and power consumption under control.
The 2011 International Technology Roadmap for Semiconductors (ITRS), finalised late last year, has been publicly released.
The roadmap looks at the problems facing the chipmaking industry from now until 2026 and includes some updates that focus on low-power design. The slides prepared by Andrew Kahng on design, for example, show how expectations on power have changed - and in a quite a big way since the last update.
One of the biggest contributors to leakage power in advanced processes is variability and the need to use guard banding to avoid having a chip fail because critical paths wind up in 'cold' high-delay parts of the die.
It's the 40th anniversary of the Intel 4004 today, the microprocessor that kicked off the microprocessor revolution. Built on NMOS, it suffered 'leakage' far more heavily than any of today's processors and its power consumption figures put in perspective just how far the industry has come.
Historically, the Interational Electron Device Meeting (IEDM) has been a forum for chipmakers to unveil their fastest, densest processes. The emphasis has been shifting steadily away from peak speed to more of a tradeoff between power and performance, with several papers reflecting the need to move away from traditional transistor metrics such as current drive.
IBM and STMicroelectronics have recommended, in the past, an approach that looks more at parasitics such as drain-induced barrier lowering (DIBL), as this has a greater effect on performance in all but the fastest, most power-hungry logic circuits. NXP Semiconductor and TSMC worked together in the past decade using simulation to tune devices for real-world circuits rather than ultimate, single-device performance. This kind of work will form the basis of a session at the 2011 IEDM in Washington, DC on circuit and device interaction.
Process variability does not immediately sound as though it has an impact on low-power design, but it has several insidious consequences. And it's gradually getting to be more of a problem.
Variability causes higher power consumption because of the way it can shift the threshold voltage, which can make transistors a lot leakier than they should be. Typically, the leakage current of an integrated circuit has a log-normal distribution; increased variability will drive the leakage up because on its effect on that log-normal curve.
Variability also limits how far you can drive the supply voltage down because as the six-sigma variation in transistor threshold voltage approaches the supply, you lose the ability to lower the supply voltage any further.
Mainstream CMOS process development is a little like Highlander: there can be only one. It matters which choices other chipmakers make because they will control how quickly the industry as a whole can get down the yield learning curve - and how much the end product costs.
It is possible to use more exotic processes but these really only succeed in markets where regular CMOS does not work at all well or the products command enough of a premium to overcome the problem of dealing with a smaller supplier base. AMD and IBM, for example, have pushed silicon-on-insulator (SOI) for a number of years.
AMD had to take lower margins than Intel, which favoured mainstream bulk CMOS, but the PC processor business still has pretty good margins, particularly at the high end. IBM wanted the performance offered by partially depleted SOI in its mainframe processors. Elsewhere, SOI was restricted to specialty products such as hearing-aid chips and very low-voltage power converters.
Today, designers are faced with the prospect of the Highlander principle coming to an end, or at least experiencing a temporary reprieve. To some extent it has already happened. Bulk CMOS processes have yet to go completely over to high-k, metal-gate processes in favour of the old poly-oxynitride gates. The option chosen by Intel is significantly more expensive and only provides clear benefits - in the 30nm to 40nm range at least - for high clock-speed designs rather than low-power sub-gigahertz designs.
The choice between the successors to the bulk planar transistor could split along similar lines, although the impact on cost of each is less clear cut. And the decision for designers may hinge on how many terminals you want in a transistor, based on the consensus at a panel at last week's Semicon West.
The Design Automation Conference, which returns to San Diego this year, is now less than a month away and has put together a programme that includes coverage of low-power design issues.
Tuesday 7 June has a panel that attempts to work out who in the design chain can make the biggest savings, from device physicists to systems and software engineers. The "who could?" is pretty easy to answer; the tricky bit is the "who will?".
In days of yore, one process used to fit them all. Then CMOS processes split into high-power (HP) and low-power (LP) process options. As 3D transistors such as the finFETs that Intel will deploy at 22nm become more common, we can expect even more options to appear.
Former Electronic Engineering editor Ron Neale has tracked the progress of phase-change memory (PCM) for many years. His work on the technology dates back to when it was first proposed as a rad-hard memory for the military. Since then, PCM has promised to become a universal, low-power memory but, some 40 years, on has still failed to achieve it.
When Panasonic said it would ship its first parts based on a 32nm high-k, metal-gate process by last October, technical analyst firm Dick James of Chipworks was confident the company would hit its deadline and beat many of the other companies planning HKMG.
It took a while but James says Chipworks has now found a Panasonic part that uses the gate-first HKMG process - in contrast to the gate-last process used by Intel for its PC processors. Although the HKMG structure lowers gate leakage, it has typically been deployed on high-power parts because it makes more of a difference there to overall performance - and subthreshold leakage is a bigger concern to those worried about energy consumption anyway. Many planning 28nm and 32nm low-power parts reckon it's still possible to stick with regular silicon oxynitride gates.
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