Recently in System-level design Category

Normally, silicon scaling is a good thing. Except when you are making power devices, as people working in the automotive semiconductor business explained at the Design Automation and Test in Europe (DATE) conference this week in Dresden.

Klaus Meder, president of the automotive electronics division at Robert Bosch, explained in his keynote speech that denser devices are causing headaches when it comes to ensuring the reliability of power semiconductors in cars. He showed heat maps of old versus new parts and how lower silicon area is causing stronger hot spots to build on the devices. This is not good news for an industry that is expecting to put a lot more electronics into cars.

The Texas Instruments MSP430 is practically synonymous with low-power processors and, although the company may not care much for the idea of clones of the architecture appearing, that is being helped by a crop of research processors that explore the limits of the threshold voltage of CMOS transistors.

These designs are helping to push the MSP430 into lower-power territory than even the 'Wolverine' that was first unveiled just over a year ago at the 2011 International Solid State Circuits Conference (ISSCC) and which coupled a 130nm - running with reasonably conventional supply voltages - together with the company's ferroelectric memory technology as a more energy-efficient alternative to flash. The chip was launched by TI as a commercial product earlier today.

The electronic edition of the winter issue of Chip Design magazine contains a round table discussion about rapid prototyping and the interview wastes no time in asking about the technique's role in low-power design, which is not quite a direct one yet.

EETimes has put a video on YouTube that shows short excerpts from the keynote given by HP Labs' Prith Banerjee at the recent DesignCon in California where he talks about the work being done there to use optical interconnect to take backplane speeds from 10 to 300GB/s and higher and drop their power consumption.

Low-Power Engineering has posted the last instalment of its round-table interviews on making software more energy efficient and some of the problems that face an industry that needs to expose low-level hardware details through a compiler-insulated interface.

Carbon Design Systems has produced a site that makes it possible to download transaction-level models for use in system-level simulation to let designers see how IP cores will perform, and potentially feed into high-level power analysis using, as John Blyler notes in his blog, sites such as ChipEstimate.

Transaction-level modelling and system-level analysis are important tasks for any low-power design activity given the major savings that can be made at this level: simply stopping transactions from repeating needlessly pays big in terms of reducing circuit activity and, with it, energy usage.

So, a new release in the SystemC world is something to watch and version 2.3 of the library is the first to make its way towards public access since the merger of Accellera and the Open SystemC Initiative (OSCI). Accellera has put up an early version of the v2.3 library for public review to work out whether some of it needs to change to work with the latest version of the language standard - IEEE 1666-2011 - to be published this month:

It's the season for predictions and Brian Bailey, writing at EDN points out some power-related issues among other predictions made by some of the people he asked.

Linus Torvalds has signed off on the latest release of the Linux kernel, version 3.2, and it contains several additions aimed at power-management. The new code modules have been submitted over the past year by engineers working at Samsung and Texas Instruments, among others.

Linux 3.1, completed late last year, also included some tools for power monitoring: cpupowerutils. The latest batch of additions focus on ways to improve how the kernel deals with systems that use dynamic voltage and frequency scaling (DVFS), extending power management to more devices in the system than just the CPU.

When looking at new architectures for low-power operation, it is easy to get fixated on one part of the design and ignore the ramifications for the rest of the system. The consequences of that are demonstrated in a paper that was presented at last year's International Symposium on Low-Power Electronic Design in Japan.

Rami Abdallah, Pradeep Shenoy, Naresh Shanbhag and Philip Krein from the University of Illinois at Urbana-Champaign looked at how dynamic voltage scaling affects not just processors and logic but the DC/DC converter used to supply power to the circuitry, and found that the minimum energy point is not where you expect to find it.

With its Consumer Electronics Show in Las Vegas looming, the Consumer Electronics Association has published figures claiming that electronic devices still account for a relatively small share of the electricity consumption in the average US home. Or at least they did in 2010.

The figures were put together by the Fraunhofer Center for Sustainable Energy Systems based on data collected during 2010. The study found that consumer electronics accounted for about 13 per cent of a US home's electricity usage, despite there being around 25 active devices in the average household.

At his View from the Top blog, Achim Nohl writes about the longstanding problem of software failing to take advantage of the power-saving facilities offered by hardware, if not subverting them entirely.

The key in his view, and it's hard to disagree lies in providing better information on power consumption to the software engineers as they write, test and debug code: "The underlying execution target needs to expose the energy consumed by the different components that make up the system - over time and ideally through the perspective of software activity." It sounds easy enough but...

To paraphrase Everett McGill in the entertainingly rubbish actioner Under Seige 2, assumption is the mother of, ahem, problems to come. In embedded system design, it's easy to make assumptions that only have to be slightly off to confound expectations and complicate the job of optimising. That's why modelling at the system level is becoming so important - and transaction-level modelling (TLM) is doing a good job of bridging the gap between assumption and reality.

One of the ways to reduce power consumption in processor subsystems is to cut the amount of energy that it takes to shovel data from memory into the processor. The parasitic capacitance and inductance of high-speed buses contribute a lot to the overall power budget for accesses that need to bypass the on-chip caches. If you move the memory devices much closer to the processor, you can cut those parasitics dramatically.

The Low-Power Engineering Community has published the last instalment of its round table discussion on bringing architectural decisions into low-power design with some thoughts on what is needed in tools and whether power is the factor that finally forces the majority of chip-design teams to use high-level synthesis extensively.

Around the table were: Mike Meyer, a Cadence fellow; Grant Martin, chief scientist at Tensilica; Vic Kulkarni, senior vice president and general manager at Apache Design; Shawn McCloud, vice president of marketing at Calypto; and Brett Cline, vice president of marketing at sales at Forte Design Systems.

The problem, it seems, is not necessarily in tools themselves but the gaps between them.

The Energy Micro EFM32 and ARM Cortex-A15 attack very different parts of the embedded-systems market but they have considerable similarities in the way that their developers attack the problem of power consumption, as two recent overview articles at EETimes Designline show. The secret is in what the processors don't run.

At the recent Multicore Challenge II held in Bristol, Marco Cornero, a fellow in ST-Ericsson's advanced computing group gave an overview of the company's progress so far in using multicore processing for mobile systems and quantified some power savings that they have achieved so far.

At the moment, the focus is on dual-core systems largely because the existing code base for functions such as web browsing and even for video decoding was developed for uniprocessor systems. According to Cornero, quad-core is the future but practical results in terms of bang for buck are better for dual-core implementations. As low as power management is working, however, even with modest speedups on dual-core symmetric multiprocessing implementations, power consumption is dramatically better.

Writing on EETimes Design, Joseph Yiu of ARM has described some techniques for using the low-power modes of the Cortex-M0 microcontroller core.

The M0 supports two basic sleep modes: a normal and a deep-sleep mode that reduce power to memory and shuts down more of the peripherals. Yiu describes ways to attach interrupts to wake-up events so that the programmer can control what will take the processor out of sleep mode.

The British Engineering Excellence Awards were held yesterday at the Globe Theatre in London and some of the finalists showed the benefits of focusing on energy-efficient in some unsual areas.

The BEEAs have a category dedicated to green products from all areas of engineering - the winner was a microwave-based system that reduced the power needed to process a fireproofing material. However, one of the finalists was TDK-Lambda which put forward an energy-saving power supply. The increase in average efficiency was good enough to able to remove a noisy fan and rely entirely on ambient cooling. In addition, the company has added increasing amounts of software to its PSU designs to be able to upgrade the power-conversion algorithms as they improve.

Researchers are finding novel ways to harness energy from the environment - as well as from people - although the levels remain so tiny that it the harvesting process will put a lot of pressure on low-power circuit design for some time to come.

The latest idea comes from the University of Wisconsin-Madison where assistant professor Xudong Wang and colleagues have developed a piezoelectric harvester that can be driven by a person's breathing. The researchers built a tiny belt using polyvinylidene fluoride that when flexed by air passing over it generates a small current.

In the meantime, researchers at MIT claim to have found a way to extend the usefulness of vibration harvesting. Most vibration-powered systems rely on resonance to work, which implies there is a peak frequency at which the system derives most of its energy. Move away from the resonant frequency, and the efficiency of the harvester plummets.