“In a few years, it’s just going to be ASSPs and FPGAs,” he says, “ASICs are going to disappear.”
“The barriers to doing ASICs, technically and financially, are becoming almost insurmountable,” he says, “by definition, if they don’t hit first time they miss half the market and, if they miss twice, they miss all the market.”
“The ASIC world used to be subsidised heavily by Japanese IDMs,” says Gavrielov, “as they depart and give up their own manufacturing and go to TSMC, you don’t get any advantage in going to a Japanese ASIC manufacturer. ST are still there but I think it’s a very painful business for them.”
The company’s 20m ASIC gate FPGA uses 2.5D stacking to put four FPGA die aligned side by side on a silicon interposer. The interposer includes over 10,000 high speed interconnects between each die.
Asked why the ASIC vendors couldn’t follow suit with a 2.5D stacked silicon approach of their own, Gavrielov, replies: “We think we have the right architecture and the tool flow to support it. We provide the tools that enable it, and that’s a big deal. If you have to go out and beg for the tools, that’s not attractive.”