Some programmable start-ups like Achronix and MathStar have come along, but they've sought out high performance markets.
Little, seemingly, has been done to address the main disadvantages of programmables - that they are too expensive and use too much power.
Now TierLogic has come up with a monolithic FPGA/ASIC chip which at least addresses one of those problems.
"It's the first monolithic 3D FPGA - an FPGA and ASIC in a single die", says TierLogic's Paul Hollingworth.
Whether used as an FPGA, an ASIC or for FPGA-ASIC conversion, the chip cuts cost.
As an FPGA, TierLogic's chip is half the cost of high-end FPGAs, and 20% lower than low-end FPGAs and, as an ASIC, the chip s 50% cheaper than conventional ASIC with an NRE of under $25,000
"There hasn't been much innovation in the last couple of decades," says Hollingworth, "the programmable companies have driven down Moore's Law but they haven't innovated."
One of the encouraging things about TierLogic is that its approach is based on innovations in process technology.
The TierLogic chip uses nine layers of metal which hold the core logic array, over which the configuration SRAM transistors are held in an amorphous silicon TFT layer on top of the metal layers.
"Metal 9 is the layer that is changed", says Hollingworth, "all we use the TFT for is to store a static 1 or 0 as a latch."
When delivering and ASIC the TFT configuration layer is stripped out leaving the customer's logic to be fabbed. Wafers up to Metal 8 are stored and to give a four week TAT.
Why 3D? "Because scaling is only going so far and it will be so expensive - ruinously expensive," replies Hollingworth, "if you can offer the same density as the technology two nodes earlier on the process curve, why don't you?"
"Building skyscrapers is a good use of land because building materials are cheap."