Will Flexible ASSPs Meet Up With Fixed Function FPGAs?

With the programmable companies adding more and more fixed functionality to their FPGAs, and the ASSP people making their chips more programmable, when will these two product segments meet in the middle?

“ASSPs are becoming more flexible, and there are areas where we meet, but we make sure our products scale in all sorts of directions,” replies Mark Dickinson, Altera’s vp for systems solutions engineering.

The programmables have a big advantage, reckons Dickinson: “The ASSP people don’t know how to do hardware programming.”

Couldn’t the ASSP people just poach a few Altera guys and find out?

“They could, but it would take them 100 man-years of effort,” replies Dickinson, “and their software support would be so inferior it’s not true.”

“A lot of our hardware remains programmable,” adds Dickinson, “we stay true to our programmable roots. For instance the hardware transceivers we put on our FPGAs are very adaptable.”

Dickinson concludes: “The ASSP people can’t meet that – not on the trajectory they’re on.”



  1. FPGAs do have some major advantages, not least of which is the widespread programming and support infrastructure (and economy of scale).
    Any reprogrammable ASSP (e.g. dynamically reconfigurable logic) has the problem of how to get the customer’s design onto the hardware, using tools which may be immature or unable to accept the format that the design is in.
    Both FPGA and reconfigurable logic do have the huge advantage over fixed-function ASSPs that they can be changed afterwards (and quickly), and manufactured before the algorithms are even finalised.
    But there is a power (and area) penalty to be paid for flexibility, which is significant (maybe 2x-3x) for reconfigurable logic and large (maybe 5x-10x) for FPGA, compared to fixed function logic in the same process.
    For applications which just can’t afford this extra power (or cost) FPGAs aren’t the answer, even though the NRE costs are drastically lower. Even the fact that they may be in a newer process node doesn’t help so much nowadays, it would take maybe 4-5 process generations (6-10 years) for FPGA power and area to catch up with hardwired ASSP logic.
    Maybe reconfigurable logic ASSPs can fill the gap, giving some of the FPGA advantages (flexibility, shorter development time) without such a big cost in power consumption. But they still have the software/coding/programming problem to solve, and this is a steep cliff to climb given the industry investment in tools for ASIC/ASSP and FPGA and the familiarity of these to users.

  2. “They could, but it would take them 100 man-years of effort,”
    Poach 100 Altera guys then – job sorted !!!

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